FPGA switch block layout and evaluation

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2002, Pages 11-18

  Schmit, Herman ^a   Chandra, Vikas ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

FPGA Interconnect; VLSI Layout

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; MATRIX ALGEBRA; VLSI CIRCUITS;

SWITCH BLOCK ARCHITECTURES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036382633     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/503048.503051     Document Type: Conference Paper

References (13)

1. V. Betz and J. Rose. Automatic generation of FPGA routing architectures from high-level descriptions. In 8th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, (FPGA 2000), pages 175-184, Feb. 2000.
2. V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs, chapter 7. Kluwer Academic Publishers, 1999.
3. S. Brown, M. Khellah, and Z. Vranesic. Minimizing FPGA interconnect delays. IEEE Design and Test of Computers, pages 16-23, Dec. 1996.
4. Y.-W. Chang, D. F. Wong, and C. K. Wong. Universal switch blocks for FPGA design. ACM Transactions Design Automation of Electronic Systems, 1(1):80-101, Jan. 1996.
5. H. Fan, J. Liu, Y.-L. Wu, and C.-C. Cheung. On optimum switch box designs for 2-D FPGAs. In Proceedings of the 38th ACM/SIGDA Design Automation Conference (DAC), pages 201-208, June 2001.
6. P. Hallschmid and S. Wilton. Detailed routing architectures for embedded programmable logic IP cores. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 69-74, Feb. 2001.
7. M. Khellah, S. Brown, and Z. Vranesic. Minimizing interconnection delays in array-based FPGAs. In Proceedings of the IEEE 1995 Custom Integrated Circuits Conference (CICC), pages 181-184, May 1994.
8. G. Lemieux, S. Brown, and D. Vranesic. On two-step routing for FPGAs. In Proceedings of the 1997 International Symposium on Physical Design, pages 60-66, Apr. 1997.
9. W.J. LeVeque. Elementary Theory of Numbers. Dover, 1960.
10. M.I. Masud and S. Wilton. A new switch block for segmented FPGAs. In International Workshop on Field Programmable Logic and Applications, Aug. 1999.
11. J. Rose and S. Brown. Flexibility of interconnection structures for field-programmable gate arrays. IEEE Journal of Solid State Circuits, 26(3):277-282, Mar. 1991.
12. S. Wilton. Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory. PhD thesis, University of Toronto, 1997.
13. Xilinx Inc. The Programmable Logic Data Book. 1994.