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Volumn , Issue , 2003, Pages 204-209

Fishbone: A block-level placement and routing scheme

Author keywords

Placement; Routing

Indexed keywords

MATHEMATICAL MODELS; PROBLEM SOLVING; TREES (MATHEMATICS); VLSI CIRCUITS;

EID: 0038040144     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (7)

References (9)
  • 4
    • 0034784797 scopus 로고    scopus 로고
    • Scaling scenario of multi-level interconnects for future CMOS LSI
    • Symposium on VLSI Technology
    • H. Yoshimura, Y. Asahi and F. Matsuoka, "Scaling Scenario of Multi-level Interconnects for Future CMOS LSI", Digest of Technical Papers, Symposium on VLSI Technology, 2001, pages 143-144.
    • (2001) Digest of Technical Papers , pp. 143-144
    • Yoshimura, H.1    Asahi, Y.2    Matsuoka, F.3
  • 7
    • 0031269743 scopus 로고    scopus 로고
    • Accuracy and fidelity of fast net length estimates
    • Nov
    • J.L.Ganley, "Accuracy and Fidelity of Fast Net Length Estimates", ACM VLSI Integration, the VLSI Journal, vol.23, no.2, Nov, 1997, pages 151-155.
    • (1997) ACM VLSI Integration, the VLSI Journal , vol.23 , Issue.2 , pp. 151-155
    • Ganley, J.L.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.