A general approach for the performance assessment of nanoscale silicon FETs

IEEE Transactions on Electron Devices

Volumn 51, Issue 9, 2004, Pages 1366-1370

  Wang, Jing ^a   Solomon, Paul M ^a   Lundstrom, Mark ^a  

^a IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROSTATIC INTEGRITY; GATE CONTROL; NANOSCALE SILICON FIELD EFFECT TRANSISTORS; NONPLANAR WIRE STRUCTURES; QUANTUM CONFINEMENT; SHORT CHANNEL EFFECT;

ELECTROSTATICS; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; QUANTUM THEORY; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR QUANTUM WIRES; SILICON WAFERS;

GATES (TRANSISTOR);

EID: 4444266909     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.833962     Document Type: Article

References (16)

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