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Volumn 4, Issue , 2001, Pages 754-757
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ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique
a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
CMOS PROCESSS;
CMOS TECHNOLOGY;
ESD LEVEL;
ESD PROTECTION;
ON-CHIP ESD PROTECTION;
SALICIDES;
CMOS INTEGRATED CIRCUITS;
ELECTROSTATIC DISCHARGE;
SUBSTRATES;
ELECTROSTATIC DEVICES;
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EID: 84888038303
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ISCAS.2001.922347 Document Type: Conference Paper |
Times cited : (20)
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References (7)
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