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Volumn 4, Issue , 2001, Pages 754-757

ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; CMOS TECHNOLOGY; ESD LEVEL; ESD PROTECTION; ON-CHIP ESD PROTECTION; SALICIDES;

EID: 84888038303     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922347     Document Type: Conference Paper
Times cited : (20)

References (7)
  • 2
    • 33747060861 scopus 로고
    • Achieving uniform nMOS device power distribution for sub-micron ESD reliability
    • C. Duwury, et al., "Achieving uniform nMOS device power distribution for sub-micron ESD reliability," Tech. Dig. of IEDM, 1992, pp. 131-134.
    • (1992) Tech. Dig. of IEDM , pp. 131-134
    • Duwury, C.1
  • 3
    • 0026838967 scopus 로고
    • Dynamic gate coupling of NMOS for efficient output ESD protection
    • C. Duwury. et al., "Dynamic gate coupling of NMOS for efficient output ESD protection." Proc. of IRPS, 1992. pp. 141-150.
    • (1992) Proc. of IRPS , pp. 141-150
    • Duwury, C.1
  • 4
    • 0031352418 scopus 로고    scopus 로고
    • Design methodology for optimizing gate driven ESD protection circuits in submicron CMOS processes
    • J. Chen, et al., "Design methodology for optimizing gate driven ESD protection circuits in submicron CMOS processes," Proc. of EOS/ESD Symp. 1997. pp. 230-239.
    • (1997) Proc. of EOS/ESD Symp , pp. 230-239
    • Chen, J.1
  • 5
    • 0032316866 scopus 로고    scopus 로고
    • ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration
    • W. Anderson, et al., "ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration," Proc. of EOS/ESD Symp., 1998. pp. 54-62.
    • (1998) Proc. of EOS/ESD Symp , pp. 54-62
    • Anderson, W.1
  • 6
    • 0032599280 scopus 로고    scopus 로고
    • Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35um silicided process
    • T.-Y. Chen, et al. "Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35um silicided process." Proc. of Int. Symp. on VLSI Technology, System, and Application, 1999. pp.35-38.
    • (1999) Proc. of Int. Symp. on VLSI Technology, System, and Application , pp. 35-38
    • Chen, T.-Y.1
  • 7
    • 0033281247 scopus 로고    scopus 로고
    • A 0.18 urn CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications
    • C. Diaz, et al. "A 0.18 urn CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications." Proc. of Symp. on VLSI Tech., 1999, pp.11-12.
    • (1999) Proc. of Symp. on VLSI Tech , pp. 11-12
    • Diaz, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.