Resonant clocking using distributed parasitic capacitance

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 9, 2004, Pages 1520-1528

  Drake, Alan J ^a   Nowka, Kevin J ^a   Nguyen, Tuyet Y ^a   Burns, Jeffrey L ^b   Brown, Richard B ^c  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c UNIVERSITY OF UTAH   (United States)

Author keywords

Clock generator; Energy recovery circuit; Harmonic resonance; Low power

Indexed keywords

CLOCK GENERATORS; ENERGY-RECOVERY CIRCUIT; HARMONIC RESONANCE; LOW POWER;

CAPACITORS; ELECTRIC CLOCKS; ELECTRIC INDUCTORS; FREQUENCIES; JITTER; NEGATIVE RESISTANCE; NETWORKS (CIRCUITS); OSCILLATIONS; RESONANCE; SWITCHING; VARIABLE FREQUENCY OSCILLATORS;

MICROPROCESSOR CHIPS;

EID: 4444261754     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.831435     Document Type: Conference Paper

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