Active GHz clock network using distributed PLLs

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1553-1560

  Gutnik, Vadim ^a,b,c,d   Chandrakasan, Anantha P ^a,c,d  

^a Massachusetts Institute of Technology Cambridge   (United States)

^b SILICON LABORATORIES   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE NETWORKS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT TESTING; LINEAR SYSTEMS; MATRIX ALGEBRA; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; SYNCHRONIZATION;

CLOCK NETWORK; LARGE SIGNAL STABILITY; PHASE DETECTORS; SMALL SIGNAL STABILITY;

TIMING CIRCUITS;

EID: 0034316214     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881199     Document Type: Article

References (9)

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