On-chip power-grid simulation using latency insertion method

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 3, 2008, Pages 914-931

  Lalgudi, Subramanian N ^a   Swaminathan, Madhavan ^a   Kretchmer, Yaron ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b ALTERA CORPORATION   (United States)

Author keywords

Computational complexity; Explicit; Floating capacitor; Implicit; Latency insertion method (LIM); Power distribution network (PDN)

Indexed keywords

CAPACITANCE; CAPACITORS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC POWER SYSTEMS; EQUIVALENT CIRCUITS;

FLOATING CAPACITOR; LATENCY INSERTION METHOD (LIM); ON-CHIP POWER-GRID SIMULATION; POWER DISTRIBUTION NETWORK (PDN);

ELECTRIC POWER DISTRIBUTION;

EID: 44349184337     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.918223     Document Type: Article

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