Impact of low-impedance substrate on power supply integrity

IEEE Design and Test of Computers

Volumn 20, Issue 3, 2003, Pages 16-22

  Panda, Rajendran ^a   Sundareswaran, Savithri ^a   Blaauw, David ^b  

^a MOTOROLA INC   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DIGITAL CIRCUITS; DOPING (ADDITIVES); ELECTRIC IMPEDANCE; MOS DEVICES; SUBSTRATES;

VOLTAGE FLUCTUATIONS;

POWER SUPPLY CIRCUITS;

EID: 0038044547     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1198681     Document Type: Review

References (6)

1. R. Panda et al., "On the Interaction of Power Distribution Network with Substrate," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED 01), ACM Press, 2001, pp. 388-393.
2. R. Panda et al., "Model and Analysis for Combined Package and On-Chip Power Grid Simulation," Proc. Int'l. Symp. Low Power Electronics and Design (ISLPED 00), ACM Press, 2000, pp. 179-184.
3. M. Felder and J. Ganger, "Analysis of Ground-Bounce Induced Substrate Noise Coupling in a Low Resistive Bulk Epitaxial Process: Design Strategies to Minimize Noise Effects on a Mixed-Signal Chip," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 11, Nov. 1999, pp. 1427-1436.
4. A. Dharchoudhyry et al., "Design and Analysis of Power Distribution Networks in PowerPC Microprocessors," Proc. 35th Design Automation Conf. (DAC 98), ACM Press, 1998, pp. 738-743.
5. L.T. Pillage, R.A. Rohrer, and C. Visweswariah, Electronic Circuit and System Simulation Methods, McGraw Hill Professional, 1995.
6. M. Zhao et al., "Hierarchical Analysis of Power Distribution Networks," Proc. 37th Design Automation Conference (DAC 00), ACM Press, 2000, pp. 150-155.