Serial and parallel FPGA-based variable block size motion estimation processors

Journal of Signal Processing Systems

Volumn 51, Issue 1, 2008, Pages 77-98

  Li, Brian M H ^a   Leong, Philip H W ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Bit serial; FPGA; Motion estimation; Systolic; Video compression

Indexed keywords

BANDWIDTH; BLOCK CODES; COMPUTATION THEORY; IMAGE CODING; MOTION ESTIMATION;

BLOCK MATCHING; MOTION VECTOR PREDICTION; SUM OF ABSOLUTE DIFFERENCE (SAD);

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 43449113574     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-007-0143-9     Document Type: Article

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