Low-power parallel tree architecture for full search block-matching motion estimation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Lin, Siou Shen ^a   Tseng, Po Chih ^a   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; IMAGE CODING; IMAGE COMPRESSION; MOTION COMPENSATION; MOTION ESTIMATION;

BLOCK MATCHING; LOW POWER PARALLEL TREE ARCHITECTURE; VIDEO QUALITY;

VIDEO SIGNAL PROCESSING;

EID: 4344703574     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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