An optimized systolic array architecture for full search block matching algorithm and its implementation on FPGA chips

3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005

Volumn 2005, Issue , 2005, Pages 327-330

  Mohammadzadeh, Masoud ^a   Eshghi, Mohammad ^a   Azadfar, M Mahdy ^b  

^a SHAHID BEHESHTI UNIVERSITY   (Iran)

^b IRAN TELECOMMUNICATION RESEARCH CENTER   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY ARCHITECTURE; BLOCK MATCHING; OPERATING FREQUENCY;

ALGORITHMS; CHIP SCALE PACKAGES; OPTIMIZATION; PATTERN MATCHING; REAL TIME SYSTEMS; SYSTOLIC ARRAYS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33745802577     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2005.1496700     Document Type: Conference Paper

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