A Time-Interleaved Track hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 329-332

  Louwsma, Simon M ^a   Van Tuijl, Ed J M ^a   Vertregt, Maarten ^a,b   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

GOOD TIMING; HIGH BANDWIDTH; INPUT FREQUENCY; MULTI CHANNEL; SINGLE CHANNELS; SUB-SAMPLING; TIME-INTERLEAVED; TRACK-AND-HOLD;

INTEGRATED CIRCUITS;

EID: 41549152912     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405745     Document Type: Conference Paper

References (7)

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3. S. M. Louwsma, E. J. M. van Tuijl, M. Vertregt, P. C. S. Scholtens and B. Nauta, "A 1. 6 GS/s, 16 times interleaved track & hold with 7. 6 ENOB in 0. 12 m CMOS, " Proc. ESSCIRC, pp 343-346, Sept 2004
4. K. Nagaraj et al., "A Dual-Mode 700-Msample/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0. 25 m Digital CMOS Process, " IEEE JSSC, vol. 35, pp 1760-1768, Dec 2000
5. S. M. Louwsma, E. J. M. van Tuijl, M. Vertregt and B. Nauta, "A 1. 35 GS/s, 10b, 175 mW Time-Interleaved AD Converter in 0. 13 m CMOS, " in Proc. 2007 Symp. VLSI Circuits, June 2007, in press
6. C-C. Hsu et al., "An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration, " ISSCC Dig. Tech. Papers, pp 464-465, Feb 2007
7. W. C. Black and D. A. Hodges, "Time Interleaved Converter Arrays, " IEEE JSSC, vol. SC-15, pp 1022-1028, Dec 1980