An 11b 800MS/s time-interleaved ADC with digital background calibration

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 464-466

  Hsu, Cheng Chung ^a   Huang, Fong Ching ^a   Shih, Chih Yung ^a   Huang, Chen Chih ^a   Lin, Ying Hsi ^a   Lee, Chao Cheng ^a   Razavi, Behzad ^b  

^a REALTEK SEMICONDUCTOR CORP   (Taiwan)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; GAIN CONTROL;

ANALOG TO DIGITAL CONVERTERS (ADC); DIGITAL BACKGROUND CALIBRATION;

POWER CONVERTERS;

EID: 34548831968     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373495     Document Type: Conference Paper

References (5)

1. S. Gupta, M. Choi, M. Inerfield, et.al., "A 1GS/s 11b Time-Interleaved ADC in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 576-577, Feb., 2006.
2. G. C. Luna, D.E. Crivelli, M.R. Hueda, et al., "Compensation of Track and Hold Frequency Response Mismatches in Interleaved Analog to Digital Converters for High-Speed Communications," IEEE ISCAS, pp. 1631-1634, May, 2006.
3. K. Hadidi, A. Khoei, "A Highly Linear Cascode-Driver CMOS Source-Follower Buffer," IEEE Intl. Conf. on Electronics, Circuits and Systems, pp. 1243-1246, Oct., 1996.
4. F. C. Huang, C. C. Hsu, "A Calibration Apparatus for Mismatches of Time-Interleaved Analog-to-Digital Converter," Taiwan patent pending App. no. 95127425, Jul. 27, 2006.
5. C. L. Lin, "Receiver Capable of Correcting Mismatch of Time-Interleaved Parallel ADC and Method Thereof," U.S. patent pending App. no. 11/164491, Nov. 25, 2005.