A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS

ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Volumn , Issue , 2004, Pages 343-346

  Louwsma, Simon M ^a   Van Tuijl, Ed J M ^a   Vertregt, Maarten ^b   Scholtens, Peter C S ^b   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CAPACITANCE; CAPACITORS; ELECTRIC POTENTIAL; ENERGY UTILIZATION; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; NYQUIST DIAGRAMS; SIGNAL TO NOISE RATIO; SWITCHING CIRCUITS;

FLASH CONVERTERS; INTERLEAVING; PHASE ALIGNMENT; TRACK AND HOLD (T/H) CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 17644374226     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. P. Scholtens, et al., "6-bit 1.6-Gsample/s flash ADC in 0.18-μm CMOS Using Averaging Termination," IEEE J. Solid-State Circuits, vol 37 pp. 1599 -1609, December 2002.
2. K. Poulton, et al., "A 20GS/s 8b ADC with a 1MB Memory in 0.18 μm CMOS", ISSCC Digest of Technical Papers, Feb. 2003.
3. J. C. Jensen, et al., "A Broadband 10-GHz Track-and-Hold in Si/SiGe HBT Technology", IEEE J. Solid-State Circuits, vol 37 pp. 325-330, March 2001
4. A. Boni, et al., "A 1-GS/s 2.7-V Track-and-Hold Amplifier with 10-b Resolution at Nyquist in SiGe BiCMOS", ESSCIRC, September 2001, pp 451-454.
5. 2 in 0.13μm CMOS", ISSCC Digest of Technical Papers, Feb. 2004.