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Volumn 28, Issue 12, 2007, Pages 1983-1987

Design for triple-valued NAND and NOR gates based on resonant tunneling devices

Author keywords

Multiple valued logic; NAND; NOR; RT device; Switching sequence

Indexed keywords

COMPUTER SIMULATION; SPICE; VLSI CIRCUITS;

EID: 40049105711     PISSN: 02534177     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (6)

References (19)
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  • 7
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  • 8
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    • Mazumder, P.1    Kulkarni, S.2    Bhattacharya, M.3
  • 10
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  • 11
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  • 19
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    • in Chinese
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.