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Volumn 2, Issue , 2003, Pages 520-523

A novel application of resonant tunneling devices in high performance digital circuits

Author keywords

Application software; Circuit noise; CMOS logic circuits; CMOS technology; Digital circuits; Energy consumption; Logic devices; Resonant tunneling devices; Semiconductor diodes; Voltage

Indexed keywords

APPLICATION PROGRAMS; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; DIGITAL DEVICES; ELECTRIC POTENTIAL; ENERGY UTILIZATION; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; LOGIC DEVICES; NANOTECHNOLOGY; RESONANT TUNNELING; RESONANT TUNNELING DIODES; SEMICONDUCTOR DEVICES; SEMICONDUCTOR DIODES; TEMPERATURE MEASURING INSTRUMENTS;

EID: 52149118955     PISSN: 19449399     EISSN: 19449380     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2003.1230961     Document Type: Conference Paper
Times cited : (5)

References (6)
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  • 2
    • 0000900676 scopus 로고    scopus 로고
    • Digital Circuit Applications of Resonant Tunneling Devices
    • Apr.
    • P. Mazumder, S. Kulkarni, M. Bhattacharya, et al., "Digital Circuit Applications of Resonant Tunneling Devices," Proc. IEEE, vol. 86, no. 4, pp. 664-686, Apr. 1998.
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  • 3
    • 0029253175 scopus 로고
    • Monolithic Integration of Resonant Tunneling Diodes and FET's for Monostable-Bistable Transition Logic Elements (MOBILE's)
    • Feb.
    • K. J. Chen, T. Akeyoshi, and K. Maezawa, "Monolithic Integration of Resonant Tunneling Diodes and FET's for Monostable-Bistable Transition Logic Elements (MOBILE's)," IEEE Electron Device Lett., vol. 16, pp. 70-73, Feb. 1995.
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    • Chen, K.J.1    Akeyoshi, T.2    Maezawa, K.3
  • 5
    • 84941341554 scopus 로고    scopus 로고
    • Digital Logic Gate Design Using Negative Differential Resistance Diodes and Field Effect Transistors
    • US Patent
    • S. Kulkarni, P. Mazumder, and G. I. Haddad, "Digital Logic Gate Design Using Negative Differential Resistance Diodes and Field Effect Transistors," US Patent 5903170, 1999.
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    • Kulkarni, S.1    Mazumder, P.2    Haddad, G.I.3
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    • Noise in Digital Dynamic CMOS Circuits
    • June
    • P. Larsson and C. Svensson, "Noise in Digital Dynamic CMOS Circuits," IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 655-662, June 1994.
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    • Larsson, P.1    Svensson, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.