Resonant-tunneling diode and HEMT logic circuits with multiple thresholds and multilevel output

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 2, 1998, Pages 268-274

  Waho, Takao ^a,b,d,e,f   Chen, Kevin J ^a,b,c,g,h   Yamamoto, Masafumi ^a,b,e,f,i,j  

^a IEEE   (Japan)

^b NTT CORPORATION   (Japan)

^c CITY UNIVERSITY OF HONG KONG   (Hong Kong)

^d WASEDA UNIVERSITY   (Japan)

^e Musashino Electrical Communication Lab   (Japan)

^f JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

^g PEKING UNIVERSITY   (China)

^h UNIVERSITY OF MARYLAND   (United States)

ⁱ HOKKAIDO UNIVERSITY   (Japan)

^j Quantum Effect Devices Group

more..

Author keywords

MODFET; Multivalued logic circuits; Negative resistance devices; Resonant tunnelling devices

Indexed keywords

HIGH ELECTRON MOBILITY TRANSISTORS; INTEGRATED CIRCUITS; LOGIC CIRCUITS; NEGATIVE RESISTANCE; SEMICONDUCTING INDIUM PHOSPHIDE;

MULTILEVEL OUTPUT; MULTIPLE THRESHOLDS;

TUNNEL DIODES;

EID: 0032000806     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.658629     Document Type: Article

References (23)

1. 1-xAs heterostructure at room temperature," Appl. Phys. Lett., vol. 46, no. 5, pp. 508-510, Mar. 1985.
2. 0.47As/AlAs/InAs resonant tunneling diodes," in IEDM 1989 Tech. Dig., pp. 559-562.
3. N. Shimizu, T. Nagatsuma, T. Waho, M. Shinagawa, M, Yaita, and M. Yamamoto, "InGaAs/AlAs resonant tunneling diodes with switching time of 1.5 ps," Electron. Lett., vol. 31, no. 19, pp. 1695-1697, Sept. 1995.
4. J. Söderström and T. G. Andersson, "A multiple-state memory cell based on the resonant tunneling diode," IEEE Electron Device Lett., vol. 9, pp. 200-202, May 1988.
5. R. C. Potter, A. A. Lakhani, and H. Hier, "Three and six logic states by the vertical integration of InAlAs/InGaAs resonant tunneling structures," J. Appl. Phys., vol. 64, no. 7, pp. 3735-3736, June 1988.
6. F. Capasso, S. Sen, A. Y. Cho, and D. Sivco, "Resonant tunneling devices with multiple negative differential resistance and demonstration of a three-state memory cell for multiple-valued logic applications," IEEE Electron Device Lett., vol. EDL-8, pp. 297-229, July 1987.
7. S. J. Wei and H. C. Lin, "Multivalued SRAM cell using resonant tunneling diodes," IEEE J. Solid-State Circuits, vol. 27, pp. 212-216, Feb. 1992.
8. Z. X. Yan and M. J. Deen, "A new resonant-tunneling diode-based multivalued memory circuit using MESFET depletion load," IEEE J. Solid-State Circuits, vol. 27, pp. 1198-1202, Aug. 1992.
9. A. C. Seabaugh, Y. C. Kao, and H. T. Yuan, "Nine-state resonant tunneling diode memory," IEEE Electron Device Lett., vol. 13, pp. 479-481, Sept. 1992.
10. G. Frazier, A. Taddiken, A. C. Seabaugh, and J. Randall, "Nanoelectronic circuits using resonant tunneling transistors and diodes," in 1993 IEEE Int. Solid-State Circuit Conf. TP 11.4.
11. S.-J. Wei, H. C. Lin, R. C. Potter, and D. Shupe, "A self-latching A/D converter using resonant tunneling diodes," IEEE J. Solid-State Circuits, vol. 28, pp. 697-700, June 1993.
12. T.-H. Kuo, H. C. Lin, R. Potter, and D. Schupe, "Multiple-valued counter," IEEE Trans. Comput., vol. 42, pp. 106-109, Jan. 1993.
13. L. J. Micheel, A. H. Taddiken, and A. C. Seabaugh, "Multiple-valued logic computation circuits using micro- and nanoelectronics devices," in Proc. 23rd Int. Symp. Multiple-Valued Logic, 1993. pp. 164-169.
14. K. Maezawa and T. Mizutani, "A new resonant tunneling logic gate employing monostable-bistable transition," Jpn. J. Appl. Phys. Part 2, vol. 32, no. 1A-B, pp. L42-L44, Jan. 1993.
15. K. C. Smith, "Multiple-valued logic: A tutorial and appreciation," Computer, vol. 37, no. 4, pp. 17-27, Apr. 1988.
16. K. J. Chen, T. Akeyoshi, and K. Maezawa, "Monolithic integration of resonant tunneling diodes and FET's for monostable-bistable transition logic elements (MOBILE'S)," IEEE Electron Device Lett., vol. 16, pp. 70-73, Feb. 1995.
17. K. J. Chen, K. Maezawa, T. Waho, and M. Yamamoto, "Device technology for monolithic integration of InP-based resonant tunneling diodes and HEMT's," IEICE Trans. Electron., vol. 79-C, no. 11, pp. 1515-1524, Nov. 1996.
18. T. Waho, K. J. Chen, and M. Yamamoto, "A novel multiple-valued logic gate using resonant tunneling devices," IEEE Electron Device Lett., vol. 17, pp. 223-225, May 1996.
19. K. C. Smith, "The prospects for multivalued logic: A technology and applications view," IEEE Trans. Comput., vol. C-30, pp. 619-634, Sept. 1981.
20. K. W. Current, "Current-mode CMOS multiple-valued logic circuits," IEEE J. Solid-State Circuits, vol. 29, pp. 95-107, Feb. 1994.
21. K. Maezawa, H. Matsuzaki, K. Arai, T. Otsuji, and M. Yamamoto, "High-speed operation of a resonant tunneling flip-flop circuit employing MOBILE (monostable-bistable transition logic element)," Electron. Lett., vol. 33, no. 20, pp. 1733-1734, Sept. 1997.
22. B. K. Oyama and B. P. Wong, "GaAs HBT's for analog circuits," in Proc. IEEE, vol. 81. pp. 1744-1761, Dec. 1993.
23. T. Waho and M. Yamamoto, "Application of resonant-tunneling quaternary quantizer to ultrahigh-speed A/D converter," in Proc. 27th IEEE Int. Symp. Multiple-Valued Logic, May 1997, pp. 35-40.