Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP

Journal of Parallel and Distributed Computing

Volumn 68, Issue 4, 2008, Pages 443-455

  Qiu, Meikang ^a   Sha, Edwin H M ^d   Liu, Meilin ^e   Lin, Man ^b   Hua, Shaoxiong ^c   Yang, Laurence T ^b  

^a UNO College of Engineering   (United States)

^b ST FRANCIS XAVIER UNIVERSITY   (Canada)

^c SYNOPSYS INC   (United States)

^d The University of Texas at Dallas   (United States)

^e Wright State University   (United States)

Author keywords

DSP; Loop fusion; Low power design; Partition; Schedule

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; FUNCTIONAL ANALYSIS; MULTIMEDIA SERVICES;

ENERGY MINIMIZATION; MULTIDIMENSIONAL NESTED LOOPS;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 39749088807     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jpdc.2007.06.014     Document Type: Article

References (60)

1. J.R. Allen, K. Kennedy, Vector register allocation, IEEE Trans. Comput. 41 (10) (2002) 1290-1317.
2. H. Aydin, R. Melhem, D. Mosse, P. Alvarez, Dynamic and aggressive scheduling techniques for power aware real-time systems, in: RTSS, 2001.
3. Banino C., Beaumont O., Carter L., Ferrante J., Legrand A., and Robert Y. Scheduling strategies for master-slave tasking on heterogeneous processor platforms. IEEE Trans. Parallel Distributed Systems 15 4 (2004)
4. Burd T., Pering T., Stratakos A., and Brodersen R. A dynamic voltage scaled microprocessor system. IEEE J. Solid-State Circuits 35 11 (2000)
5. Catthoor F., Wuytack S., Greef E.D., Balasa F., Nachtergaele L., and Vandecappelle A. Custom Memory Management Methodology-Exploration of Memory Organization for Embedded Multimedia System Design (June 1998), Kluwer Academic Publishers, Dordrecht
6. Chandrakasan A., Sheng S., and Brodersen R. Low-power cmos digital design. IEEE J. Solid-State Circuits 27 4 (1992)
7. Chao L.-F., LaPaugh A., and Sha E.H.-M. Rotation scheduling: a loop pipelining algorithm. IEEE Trans. Comput.-Aided Design 16 (1997)
8. Chao L.-F., and Sha E.H.-M. Static scheduling for synthesis of dsp algorithms on various models. J. VLSI Signal Process. Systems for Signal Image and Video Tech. 10 (1995)
9. J.-J. Chen, T.-W. Kuo, Multiprocessor energy-efficient scheduling for real-time tasks with different power characteristics, in: ICPP, 2005.
10. TM microprocessors, in: Symposium on VLSI Circuits, Short Course on Physical Design for Low-Power and High-Performance Microprocessor Circuits, June 2001.
11. C. Ding, K. Kennedy, Improving effective bandwidth through compiler enhancement of global cache reuse, J. Parallel and Distributed Comput. 64 (1) (2004) 108-134.
12. Dogan A., and Özgüner F. Matching and scheduling algorithms for minimizing execution time and failure probability of applications in heterogeneous computing. IEEE T. Parall. Distr. 13 3 (2002) 308-323
13. M. Fleischmann, Crusoe power management-reducing the operating power with longrun, in: The 12th HOT CHIPS Symposium, August 2000.
14. G. Gao, R. Olsen, V. Sarkar, R. Thekkath, Collective loop fusion for array contraction, in: The 5th Workshop on Languages and Compilers for Parallel Computing, August 1992.
15. Hua S., and Qu G. Voltage set-up problem for embedded systems with multiple voltages. IEEE Trans. Very Large Scale Integration (VLSI) Systems 13 7 (2005)
16. S. Hua, G. Qu, S.S. Bhattacharyya, Energy reduction techniques for multimedia applications with tolerance to deadline misses, in: ACM/IEEE Design Automation Conference (DAC), 2003.
17. S. Hua, G. Qu, S.S. Bhattacharyya, Exploring the probabilistic design space of multimedia systems, in: IEEE International Workshop on Rapid System Prototyping, 2003.
18. Intel, The Intel XScale microarchitecture, Technical Summary, 2000.
19. T. Ishihara, H. Yasuura, Voltage scheduling problem for dynamically variable voltage processor, in: ISLPED, 1998.
20. Ito K., Lucke L., and Parhi K. Ilp-based cost-optimal dsp synthesis with module selection and data format conversion. IEEE Trans. Very Large Scale Integration (VLSI) Systems 6 (1998)
21. K. Ito, K. Parhi, Register minimization in cost-optimal synthesis of dsp architecture, in: Proceedings of the IEEE VLSI Signal Processing Workshop, October 1995.
22. ITRS, International Technology Roadmap for Semiconductors, International SEMATECH, Austin, TX 〈http://public.itrs.net/〉.
23. A. Iyer, D. Marculescu, Power-performance evaluation of globally asynchronous, locally synchronous processors, in: The 29th International Symposium on Computer Architecture, May 2002.
24. M. Kandemir, S. Son, G. Chen, An evaluation of code and data optimizations in the context of disk power reduction, in: ISLPED, 2005.
25. M. Kandemir, N. Vijaykrishnan, M. Irwin, W. Ye, Influence of compiler optimizations on system power, in: Design Automation Conference (DAC), 2000.
26. K. Kennedy, K.S. Mckinley, Maximizing loop parallelism and improving data locality via loop fusion and distribution, in: Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science, vol. 768, 1993.
27. Leiserson C.E., and Saxe J.B. Retiming synchronous circuitry. Algorithmica 6 (1991)
28. Li M., and Yao F. An efficient algorithm for computing optimal discrete voltage schedules. SIAM J. Comput. 35 3 (2005)
29. M. Liu, Q. Zhuge, Z. Shao, E.H.-M. Sha, General loop fusion technique for nested loops considering timing and code size, in: CASES, 2004.
30. J. Luo, N. Jha, Static and dynamic variable voltage scheduling algorithms for real-time heterogeneous distributed embedded systems, in: VLSID, 2002.
31. Manjikian N., and Abdelrahman T.S. Fusion of loops for parallelism and locality. IEEE Transactions on Parallel and Distributed Systems 8 (1997)
32. N. Megiddo, V. Sarkar, Optimal weighted loop fusion for parallel programs, in: The 9th Annual ACM Symposium on Parallel Algorithms and Architectures, 1997.
33. Micheli G.D. Synthesis and Optimization of Digital Circuits (1994), McGraw-Hill, New York
34. Passos N., and Sha E.H.-M. Achieving full parallelism using multi-dimensional retiming. IEEE Trans. Parallel Distributed Systems 7 11 (1996)
35. Y. Qian, S. Carr, P. Sweany, Loop fusion for clustered vliw architecture, in: LCTES-SCOPES, 2002.
36. Y. Qian, S. Carr, P. Sweany, Optimizing loop performance for clustered vliw architectures, in: IEEE PACT, 2002.
37. Sakurai T., and Newton A.R. Alpha-power law mosfet model and its application to cmos inverter delay and other formulas. IEEE J. Solid-State Circuits SC-25 2 (1990)
38. H. Saputra, M. Kandemir, N. Vijaykrishnan, M.J. Irwin, J.S. Hu, C.-H. Hsu, U. Kremer, Energy-conscious compilation based on voltage scaling, in: LCTES'02, June 2002.
39. G. Semeraro, D. Albonesi, S. Dropsho, G. Magklis, S. Dwarkadas, M. Scott, Dynamic frequency and voltage control for a multiple clock domain microarchitecture, in: The 35th International Symposium on Microarchitecture, November 2002.
40. G. Semeraro, G. Magklis, R. Balasubramonian, D. Albonesi, S. Dwarkadas, M. Scott, Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling, in: The 8th International Symposium on High-Performance Computer Architecture, February 2002.
41. J. Seng, E. Tune, D. Tullsen, Reducing power with dynamic critical path information, in: MICRO 2001, 2001.
42. Shao Z., Zhuge Q., Xue C., and Sha E.H.-M. Efficient assignment and scheduling for heterogeneous dsp systems. IEEE T. Parall. Distr. 16 (2005)
43. D. Shin, J. Kim, S. Lee, Low-energy intra-task voltage scheduling using static timing analysis, in: Design Automation Conference (DAC), 2001.
44. Singhai S.K., and Mckinley K.S. A parameterized loop fusion algorithm for improving parallelism and cache locality. Comput. J. 40 6 (1997)
45. Stan M.R., and Burleson W.P. Bus-invert coding for low-power i/o. IEEE Trans. Very Large Scale Integration (VLSI) Systems 3 1 (1995)
46. Tongsima S., Sha E.H.-M., Chantrapornchai C., Surma D., and Passos N. Probabilistic loop scheduling for applications with uncertain execution time. IEEE Trans. Comput. 49 (2000)
47. S. Verdoolaege, M. Bruynooghe, F. Catthoor, Multi-dimensional incremental loop fusion for data locality, in: ASAP, 2003.
48. Wang C.-Y., and Parhi K.K. Resource constrained loop list scheduler for dsp algorithms. J. VLSI Signal Process. 11 (1995)
49. Wang Z., and Hu X. Energy-aware variable partitioning and instruction scheduling for multibank memory architectures. ACM Trans. Design Automat. of Electron. Systems (TODAES) 10 2 (2005)
50. Wolfe M.E. High Performance Compilers for Parallel Computing (1996), Addison-Wesley, Redwood City, CA
51. M.J. Wolfe, Optimizing supercompilers for supercomputers, Ph.D. Thesis, Department of Computer Science, University of Illinois at Urbana-Champaign, October 1982.
52. F. Yao, A. Demers, S. Shenker, A scheduling model for reduced cpu energy, in: The 36th Symposium on Foundations of Computer Science (FOCS), Milwankee, WI, October 1995.
53. Y. Yu, V.K. Prasanna, Power-aware resource allocation for independent tasks in heterogeneous real-time systems, in: ICPADS, 2002.
54. J. Zambreno, M. Kandemir, A. Choudhary, Enhancing compiler techniques for memory energy optimizations, in: EMSOFT, 2002.
55. W. Zhang, N. Vijaykrishnan, M. Kandermir, M. Irwin, D. Duarte, Y. Tsai, Exploiting vliw schedule slacks for dynamic and leakage energy reduction, in: MICRO 2001, 2001.
56. Y. Zhang, X. Hu, D.Z. Chen, Task scheduling and voltage selection for energy minimization, in: Design Automation Conference (DAC), 2002.
57. Zhou T., Hu X., and Sha E.H.-M. Estimating probabilistic timing performance for real-time embedded systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 6 (2001)
58. Y. Zhu, G. Magklis, M.L. Scott, C. Ding, D.H. Albonesi, The energy impact of aggressive loop fusion, in: IEEE PACT, 2004.
59. Zhuge Q., Sha E.H.-M., Xiao B., and Chantrapornchai C. Efficient variable partitioning and scheduling for dsp processors with multiple memory modules. IEEE Trans. Signal Process. 52 4 (2004)
60. Zhuge Q., Xiao B., and Sha E.H.-M. Code size reduction technique and implementation for software-pipelined dsp applications. ACM Trans. Embedded Comput. Systems 2 4 (2003)