Efficient Variable Partitioning and Scheduling for DSP Processors With Multiple Memory Modules

IEEE Transactions on Signal Processing

Volumn 52, Issue 4, 2004, Pages 1090-1099

  Zhuge, Qingfeng ^a   Sha, Edwin Hsing Mean ^a   Xiao, Bin ^a   Chantrapornchai, Chantana ^b  

^a The University of Texas at Dallas   (United States)

^b SILPAKORN UNIVERSITY   (Thailand)

Author keywords

DSP processor; Retiming; Scheduling; Variable partitioning

Indexed keywords

ALGORITHMS; COMPUTER SOFTWARE; DATA REDUCTION; FIR FILTERS; GRAPH THEORY; MICROPROCESSOR CHIPS; PROBLEM SOLVING; SCHEDULING;

DSP PROCESSORS; RETIMING; VARIABLE PARTITIONING;

DIGITAL SIGNAL PROCESSING;

EID: 1842429024     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSP.2004.823506     Document Type: Article

References (19)

1. G. Araujo, S. Devadas, K. Keutzer, S. Liao, S. Malik, A. Sudarsanam, S. Tjiang, and A. Wang, "Challenges in code generation for embedded processors," in Code Generation for Embedded Processors, P. Marwedel and G. Goossens, Eds. Boston, MA: Kluwer, 1995, ch. 1, pp. 4-17.
2. S. Y. H. Liao, "Code generation and optimization for embedded digital signal processors," Ph.D. dissertation, Mass. Inst. Technol., Cambridge, MA, 1996.
3. D. Lanneer, J. V. Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens, "CHESS: Retargetable code generation for embedded processors," in Code Generation for Embedded Processors, P. Marwedel and G. Goossens, Eds. Boston, MA: Kluwer, 1995, ch. 5, pp. 85-296.
4. Z. Wang, T. W. O'Neil, and E. H.-M. Sha, "Minimizing average schedule length under memory constraints by optimal partitioning and prefetching," J. VLSI Signal Process. Syst. Signal, Image, Video Technol., vol. 27, pp. 215-233, Jan. 2001.
5. Z. Wang, M. Kirkpatrick, and E. H.-M. Sha, "Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications," in Proc. 37th ACM/IEEE Design Automat. Conf., June.. 2000, pp. 540-545.
6. DSP56000 24-Bit Digital Signal Processor Family Manual, Motorola, Schaumberg, IL, 1996.
7. ADSP-21 000 Family Application Handbook Volume 1, Analog Devices, Inc., Norwood, MA, 1994.
8. TMS320C6000 CPU and Instruction Set Reference Guide, Texas Instruments, Inc., Dallas, TX, Oct. 2000.
9. GEPARD Family of Embedded Software Programmable DSP Core http://asic.amsint.com/databooks/digital/gepard.htm [Online]
10. R. Leupers and D. Kotte, "Variable partitioning for dual memory bank DSPs," in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., vol. 2, May 2001, pp, 1121-1124.
11. M. A. R. Saghir, P. Chow, and C. G. Lee, "Exploiting dual data-memory banks in digital signal processors," in Proc. 7th ACM Int. Conf. Architectural Support Programming Languages Operating Syst., Oct. 1996, pp. 234-243.
12. A. Sudarsanam and S. Malik, "Simultaneous reference allocation in code generation for dual data memory bank ASIPs," ACM Trans. Design Automat. Electron. Syst., vol. 5, no. 2, pp. 242-264, Apr. 2000.
13. P. R. Panda, "Memory bank customization and assignment in behavioral synthesis," in Proc. ACM/IEEE Int. Conf. Comput. Aided Des., Nov. 1999, pp. 477-481.
14. M. Lam, "Software pipelining: an effective scheduling technique for VLIW machines," in Proc. ACM Conf. Programming Language Design Implementation, June 1988, pp. 318-328.
15. L.-F. Chao, A. S. LaPaugh, and E. H.-M. Sha, "Rotation scheduling: a loop pipelining algorithm," IEEE Trans. Computer-Aided Des., vol. 16, pp. 229-239, Mar. 1997.
16. C. E. Leiserson and J. B. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, pp. 5-35, Aug. 1991.
17. J. Hennessy and D. Patterson, Computer Architecture: A Quantitive Approach, 2nd ed. San Francisco, CA: Morgan Kaufmann, 1995.
18. G. D. Micheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.
19. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. San Francisco, CA: W. H. Freeman, 1979.