Systematic and automated multiprocessor systen design, programming, and implementation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 3, 2008, Pages 542-555

  Nikolov, Hristo ^a,b   Stefanov, Todor ^a,b   Deprettere, Ed ^a,b  

^a IEEE

^b LEIDEN UNIVERSITY   (Netherlands)

Author keywords

Automated programming of multiprocessor systems on chip (MPSoC); Design automation for MPSoC; System level design

Indexed keywords

COMPUTATIONAL COMPLEXITY; EMBEDDED SYSTEMS; MULTIMEDIA SYSTEMS; PROBLEM SOLVING;

DESIGN AUTOMATION; MULTIPROCESSOR ARCHITECTURES;

COMPUTER PROGRAMMING;

EID: 39749086249     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.911337     Document Type: Article

References (36)

1. G. Martin, "Overview of the MPSoC design challenge," in Proc. DAC, Jul. 2006, pp. 274-279.
2. G. Kahn. 'The semantics of a simple language for parallel programming." in Proc. IFIP Congr., 1974, pp. 471-475.
3. T. Stefanov et al., "System design using Kahn process networks: The Compaan/Laura approach," in Proc. DATE, Feb. 2004, pp. 340-345.
4. A. Nieuwland et al., C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems. Norwell. MA: Kluwer, 2002.
5. A. Pimentel et al., "A systematic approach to exploring embedded system architectures at multiple abstraction levels," IEEE Trans. Comput., vol. 55. no. 2, pp. 99-112, Feb. 2006.
6. E. de Kock, "Multiprocessor mapping of process networks: A JPEG decoding case study," in Proc. ISSS, Oct. 2002, pp. 68-73.
7. K. Goossens et al., "Guaranteeing the quality of services in networks on chip," in Networks on Chip. Norwell, MA: Kluwer, 2003, pp. 61-82.
8. B. Dwivedi et al., "Automatic synthesis of system on chip multiprocessor architectures for process networks," in Proc. CODES+ISSS. Sep. 2004, pp. 60-65.
9. S. Verdoolaege, H. Nikolov, and T. Stefanov, "pn: A tool for improved derivation of process networks," EURASIP J. Embedded Syst., vol. 2007. no. 1, p. 19, Jan. 2007. Article ID 75947, 13 pages, DOI:10.1155/2007/75947.
10. A. Turjan et al., "Translating affine nested-loop programs to process networks," in Proc. CASES. Sep. 2004, pp. 220-229.
11. B. Kienhuis et al., "Compaan: Deriving process networks from Matlab for embedded signal processing architectures," in Proc. CODES, May 2000, pp. 13-17.
12. C. Zissulescu, T. Stefanov, B. Kienhuis, and E. Deprettere, "LAURA: Leiden architecture research and exploration tool," in Proc. FPL, Sep. 2003, pp. 911-920.
13. M. J. Rutten et al., "A heterogeneous multiprocessor architecture for flexible media processing," IEEE Des. Test Comput., vol. 19, no. 4, pp. 39-50, Jul./Aug. 2002.
14. A. Gerstlauer and D. Gajski, "System-level abstraction semantics," in Proc. ISSS, Oct. 2002. pp. 231-236.
15. A. Jerraya et al., "Programming models and HW-SW interfaces abstraction for multi-processor SoC," in Proc. DAC, Jul. 2006, pp. 280-285.
16. D. Lyonnard et al., "Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip," in Proc. DAC, Jun. 2001, pp. 518-523.
17. L. Gauthier, S. Yoo, and A. Jerraya. "Automatic generation and targeting of application specific operating systems and embedded systems software," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 11, pp. 1293-1301, Nov. 2001.
18. P. Paulin et al., "Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 7, pp. 667-680, Jul. 2006.
19. H. Yu. R. Domer, and D. Gajski, "Embedded software generation from system level design languages," in Proc. ASP-DAC, Jan. 2004, pp. 463-468.
20. P. van der Wolf, E. de Kock. T. Henriksson, W. Kruijtzer. and G. Essink, "Design and programming of embedded multiprocessors: An interfacecentric approach," in Proc. CODES+ISSS, Sep. 2004. pp. 206-217.
21. Xilinx. Inc., Xilinx Platform Studio and the Embedded Development Kit. EDK version 8.11 edition. [Online]. Available: www.xilinx.com/ ise/embedded_design_prod/platform_studio.htm
22. Altera, Inc., (2005, Dec). Quartus II Handbook Volume 4: SOPC Builder. [Online]. Available: www.altera.com/literature/quartus2/lit-qts- sopc.jsp
23. Multiprocessor Solutions With FPGAs. (2005). White paper, FPGA and Programmable Logic Journal. [Online]. Available: www.fpgajournal. com/whitepapers_2005/altera_20050224.htm
24. T. Parks, "Bounded scheduling of process networks," Ph.D. dissertation, Univ. California, EECS Dept. Berkeley, 1995. Tech. Rep. UCB/ ERL-95-105.
25. J. Buck and E. Lee, "Scheduling dynamic data flow graphs with bounded memory using the token flow model," in Proc. IEEE Conf. Acoust., Speech, Signal Process., Apr. 1993, pp. 429-432.
26. M. Geilen and T. Basten, Requirements on the Execution of Kahn Process Networks, vol. 2618. Berlin, Germany: Springer-Verlag. 2003, pp. 319-334.
27. E. de Kock et al., "YAPI: Application modeling for signal processing systems." in Proc. DAC, Jun. 2000. pp. 402-405.
28. E. A. Lee et al., "Ptolemy II: Heterogeneous concurrent modeling and design in Java," Univ. California at Berkeley, Berkeley, Tech. Rep. UCB/ERL-M99/40. 1999.
29. P. Feautrier, "Automatic parallelization in the polytope model," in The Data Parallel Programming Model, vol. 1132. Berlin, Germany: Springer-Verlag, 1996, pp. 79-103.
30. P. Feautrier, "Dataflow analysis of scalar and array references," Int. J. Parallel Program., vol. 20, no. 1, pp. 23-53, Feb. 1991.
31. P. Feautrier, "Parametric integer programming." Oper. Res., vol. 22, no. 3, pp. 243-268, Sep. 1988.
32. S. Verdoolaege et al., "Multi-dimensional incremental loop fusion for data locality," in Proc. ASAP. Jun. 2003, pp. 17-27.
33. S. Verdoolaege et al., "Analytical computation of Ehrhart polynomials: Enabling more compiler analyses and optimizations," in Proc. CASES. Sep. 2004, pp. 248-258.
34. P. Clauss et al. "Symbolic polynomial maximization over convex sets and its application to memory requirement estimation." Université Louis Pasteur, Strasbourg, France, ICPS Res. Rep. 06-04, Oct. 2006.
35. T. Stefanov and E. Deprettere. "Deriving process networks from weakly dynamic applications in system-level design," in Proc. CODES+ISSS, Oct. 2003, pp. 90-96.
36. P. Lieverse, T. Stefanov, P. van der Wolf, and E. Deprettere, "System level design with SPADE: An M-JPEG case study." in Proc. ICCAD, Nov. 2001, pp. 31-38.