Automatic synthesis of system on chip multiprocessor architectures for process networks

Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004

Volumn , Issue , 2004, Pages 60-65

  Dwivedi, Basant Kumar ^a   Kumar, Anshul ^a   Balakrishnan, M ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

Application Specific Multiprocessors; Kahn Process Networks; Partitioning

Indexed keywords

COMMUNICATION SYSTEMS; DATA REDUCTION; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MULTIPROCESSING PROGRAMS; MULTIPROCESSING SYSTEMS; PROBLEM SOLVING; RESOURCE ALLOCATION;

APPLICATION SPECIFIC MULTIPROCESSORS; DIRECTED ACYCLIC GRAPH (DAG); KAHN PROCESS NETWORKS; PARTITIONING;

COMPUTER ARCHITECTURE;

EID: 16244403353     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016720.1016737     Document Type: Conference Paper

References (21)

1. Gills Kahn. The Semantics of a Simple Language for Parallel Programming. In Proc. IFIP Congress 74. North Holland Publishing Co, 1974.
2. E. A. de Kock et al. YAPI:Application Modeling for Signal Processing Systems. In Proc. Design Automation Conference (DAC), June 2000.
3. Todor Stefanov and Ed Deprettere. Deriving Process Networks from Weakly Dynamic Applications in System-Level Design. In Proc. Int. Conf. on HW/SW Codesign and System Synthesis (CODES+ISSS), October 2003.
4. Bharat P. Dave, Ganesh Lakshminarayana, and Niraj K. Jha. COSYN: Hardware Software Cosynthesis of Heterogeneous Distributed Embedded Systems. IEEE Trans. on VLSI Systems, 7(1):92-104, March 1999.
5. Jui-Ming Chang and Massoud Pedram. Codex-dp: Co-design of Communicating Systems Using Dynamic Programming. IEEE Trans. on CAD, 19(7):732-744, July 2000.
6. Jiong Luo and Niraj K. Jha. Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. In Proc. International Conference on High Performance Computing (HiPC), December 2002.
7. Dongkun Shin and Jihong Kim. Power-Aware Scheduling of Conditional Task Graphs in Real-Time Multiprocessor Systems. In Proc. International Symposium on Low Power Electronics and Design (ISLPED), August 2003.
8. Yu-Kwong Kwok and Ishfaq Ahmad. Static Scheduling Algorithms for Allocating Directed Task Graphs to Multiprocessors. ACM Computing Surveys, 31(4):406-471, December 1999.
9. Andy D. Pimentel, Louis O. Hertzberger, Paul Lieverse, Pieter van der Wolf, and Ed F. Deprettere. Exploring embedded systems architectures with artemis. IEEE Computer, (11):57-63, November 2001.
10. E. A. de Kock. Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study. In Proc. Int. Symposium on System Synthesis (ISSS), October 2002.
11. Thomas M. Parks. Bounded Scheduling of Process Networks. PhD thesis, University of California, EECS Dept. Berkeley, 1995.
12. Twan Basten and Jan Hoogerbrugge. Efficient Execution of Process Networks. In Communicating Process Architectures, 2001.
13. J. A. Leijten, J. L. van Meerbergen, A. A. Timmer, and J. A. G. Jess. PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. In Proc. International Conference on Computer Design (ICCD), 1997.
14. J. Leijten, J. van Meerbergen, A. Timmer, and J. Jess. Stream communication between real-time tasks in a high-performance multiprocessor. In Proc. Design, Automation and Test in Europe (DATE), 1998.
15. Information technology - Generic coding of moving pictures and associated audio information: Video. ISO/IEC 13818-2, 1996.
16. Basant K. Dwivedi, Anshul Kumar, and M. Balakrishnan. Synthesis of Application Specific Multiprocessor Architectures for Process Networks. Technical report, Dept. of Computer Science & Engg., Indian Institute of Technology Delhi, 2003.
17. Manoj Kumar Jain, M. Balakrishnan, and Anshul Kumar. An Efficient Technique for Exploring Register File Size in ASIP Synthesis. In Proc. Int. Conf. on Compilers, Architectures and Synthesis for Embedded Systems (CASES), October 2002.
18. http://www.arm.com.
19. http://www.gaisler.com/leon.html.
20. Basant Kumar Dwivedi, Harsh Dhand, M. Balakrishnan, and Anshul Kumar. RPNG: A Tool for Random Process Network Generation. Technical report, Dept. of Computer Science & Engg., Indian Institute of Technology Delhi, 2004.
21. http://www.intel.com/products/server/processors.