-
2
-
-
52549109220
-
-
A|RT Designer. AdelanteTechnologies, http://www.adelantetechnologies.com.
-
-
-
-
3
-
-
0004093751
-
-
The CoreConnect Bus Architecture. IBM, 1999, http://www-3.ibm.com/chips/ techlib/techlib.nsf/tech-docs/852569B20050FF77852569910050COFB/crcon_wp.pdf
-
(1999)
The CoreConnect Bus Architecture
-
-
-
5
-
-
84893658996
-
An efficient architecture model for systematic design of application-specific multiprocessor SoC
-
Baghdadi, A., D. Lyonnard, N. Zergainoh, and A. A. Jerraya. An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC. In Proceedings of the Design, Automation and Test in Europe (DATE) Conference and Exhibition, pp. 55-62, 2001.
-
(2001)
Proceedings of the Design, Automation and Test in Europe (DATE) Conference and Exhibition
, pp. 55-62
-
-
Baghdadi, A.1
Lyonnard, D.2
Zergainoh, N.3
Jerraya, A.A.4
-
7
-
-
0028737370
-
Static scheduling of multi-rate and cyclo-static DSP applications
-
Bilsen, G., M. Engels, R. Lauwereins, and J. Peperstraete. Static Scheduling of Multi-Rate and Cyclo-Static DSP Applications. In Workshop on VLSI Signal Processing, pp. 137-146, 1994.
-
(1994)
Workshop on VLSI Signal Processing
, pp. 137-146
-
-
Bilsen, G.1
Engels, M.2
Lauwereins, R.3
Peperstraete, J.4
-
8
-
-
0031101409
-
Hardware/software co-design of digital telecommunication systems
-
Bolsens, I., H. De Man, B. Lin, K. Van Rompaey, S. Vercauteren, and D. Verkest. Hardware/Software Co-Design of Digital Telecommunication Systems. In Proceedings of the IEEE, pp. 391-418, 1997.
-
(1997)
Proceedings of the IEEE
, pp. 391-418
-
-
Bolsens, I.1
De Man, H.2
Lin, B.3
Van Rompaey, K.4
Vercauteren, S.5
Verkest, D.6
-
10
-
-
0032667769
-
Communication refinement in video systems on chip
-
Brunel, J.-Y., E. A. de Kock, W. M. Kruijtzer, H. J. H. N. Kenter, and W. J. M. Smits. Communication Refinement in Video Systems on Chip. In Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES), pp. 142-146, 1999.
-
(1999)
Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES)
, pp. 142-146
-
-
Brunel, J.-Y.1
De Kock, E.A.2
Kruijtzer, W.M.3
Kenter, H.J.H.N.4
Smits, W.J.M.5
-
11
-
-
0033685325
-
COSY communication IP's
-
Brunel, J.-Y., W. Kruijtzer, H. Kenter, F. Ptrot, L. Pasquier, E. de Kock, and W. Smits. COSY Communication IP's. In Proceedings 37th Design Automation Conference, pp. 406-410, 2000.
-
(2000)
Proceedings 37th Design Automation Conference
, pp. 406-410
-
-
Brunel, J.-Y.1
Kruijtzer, W.2
Kenter, H.3
Ptrot, F.4
Pasquier, L.5
De Kock, E.6
Smits, W.7
-
12
-
-
0010903397
-
Cosy: A methodology for system design based on reusable hardware & software IP's
-
Brunel, J.-Y., A. Sangiovanni-Vincentelli, R. Kress, and W. Kruytzer. COSY: A Methodology for System Design Based on Reusable Hardware & Software IP's. In Proceedings of the European Multimedia, Microprocessor Systems and Electronic Commerce Conference, pp. 709-716, 1998.
-
(1998)
Proceedings of the European Multimedia, Microprocessor Systems and Electronic Commerce Conference
, pp. 709-716
-
-
Brunel, J.-Y.1
Sangiovanni-Vincentelli, A.2
Kress, R.3
Kruytzer, W.4
-
13
-
-
85033660515
-
Static scheduling code generation from dynamic dataflow graphs with integer valued control signals
-
Pacific Grove, California
-
Buck, J. Static Scheduling and Code Generation from Dynamic Dataflow Graphs with Integer Valued Control Signals. In Asilomar Conference Signals Systems and Computers, Pacific Grove, California, pp. 508-513, 1994.
-
(1994)
Asilomar Conference Signals Systems and Computers
, pp. 508-513
-
-
Buck, J.1
-
14
-
-
0010764837
-
Rapido: A modular, multi-board, heterogeneous multi-processor, PCI bus based prototyping framework for the validation of soc vlsi designs
-
Busa, N., G. Alkadi, M. Verberne, R. Peset Llopis, and S. Ramanathan. RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs. In Proceedings of the 13th IEEE Workshop on Rapid System Prototyping, pp. 159-165, 2002.
-
(2002)
Proceedings of the 13th IEEE Workshop on Rapid System Prototyping
, pp. 159-165
-
-
Busa, N.1
Alkadi, G.2
Verberne, M.3
Peset Llopis, R.4
Ramanathan, S.5
-
15
-
-
0028754935
-
Global communication and memory optimizing transformations for low-power signal processing systems
-
La Jolla, CA
-
Catthoor, F., F. Fraussen, S. Wuytack, L. Nachtergaele, and H. de Man. Global Communication and Memory Optimizing Transformations for Low-Power Signal Processing Systems. In Proceedings of the IEEE Workshop on Signal Processing, La Jolla, CA, 1994.
-
(1994)
Proceedings of the IEEE Workshop on Signal Processing
-
-
Catthoor, F.1
Fraussen, F.2
Wuytack, S.3
Nachtergaele, L.4
De Man, H.5
-
16
-
-
84964426944
-
A memory management approach for efficient implementation of multimedia kernels on programmable architectures
-
Dasygenis, M., N. Kroupis, A. Argyriou, K. Tatas, D. Soudris, and N. Zervas. A Memory Management Approach for Efficient Implementation of Multimedia Kernels on Programmable Architectures. In Proceedings of the IEEE Computer Society Annual Workshop on VLSI, 2001.
-
(2001)
Proceedings of the IEEE Computer Society Annual Workshop on VLSI
-
-
Dasygenis, M.1
Kroupis, N.2
Argyriou, A.3
Tatas, K.4
Soudris, D.5
Zervas, N.6
-
17
-
-
0028448212
-
Sub-pixel motion estimation with 3-D recursive search block-matching
-
de Haan, G. and P. W. A. C. Biezen. Sub-Pixel Motion Estimation with 3-D Recursive Search Block-Matching, Signal Processing: Image Communications, vol. 6, pp. 485-498, 1995.
-
(1995)
Signal Processing: Image Communications
, vol.6
, pp. 485-498
-
-
De Haan, G.1
Biezen, P.W.A.C.2
-
18
-
-
0033682583
-
YAPI: Application modelling for signal processing systems
-
de Kock, E. A., G. Essink, W. J. M. Smits, P. van der Wolf, J.-Y. Brunel, W. M. Kruijtzer, P. Lieverse, and K. A. Vissers. YAPI: Application Modelling for Signal Processing Systems. In Proceedings of the Design Automation Conference, pp. 402-405, 2000.
-
(2000)
Proceedings of the Design Automation Conference
, pp. 402-405
-
-
De Kock, E.A.1
Essink, G.2
Smits, W.J.M.3
Van Der Wolf, P.4
Brunel, J.-Y.5
Kruijtzer, W.M.6
Lieverse, P.7
Vissers, K.A.8
-
19
-
-
0032048776
-
Codesign of embedded systems: Status and trends
-
Ernst, R. Codesign of Embedded Systems: Status and Trends. In IEEE Design & Test of Computers, pp. 45-54, 1998.
-
(1998)
IEEE Design & Test of Computers
, pp. 45-54
-
-
Ernst, R.1
-
25
-
-
0000087207
-
The semantics of a simple language for parallel programming
-
J. L. Rosenfeld, Ed., North-Holland Publishing Co.
-
Kahn, G. The Semantics of a Simple Language for Parallel Programming. In Information Processing, J. L. Rosenfeld, Ed., North-Holland Publishing Co., 1974.
-
(1974)
Information Processing
-
-
Kahn, G.1
-
27
-
-
0034428118
-
System-level design: Orthogonalization of concerns and platform-based design
-
Keutzer, K., S. Malik, R. Newton, J. M. Rabaey, and A. Sangiovanni-Vincentelli. System-Level Design: Orthogonalization of Concerns and Platform-Based Design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, pp. 1523-1543, 2000.
-
(2000)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.19
, pp. 1523-1543
-
-
Keutzer, K.1
Malik, S.2
Newton, R.3
Rabaey, J.M.4
Sangiovanni-Vincentelli, A.5
-
29
-
-
84939698077
-
Static scheduling of synchronous data flow graphs for digital signal processors
-
Lee., E. A. and D. G. Messerschmidt. Static Scheduling of Synchronous Data Flow Graphs for Digital Signal Processors. In Proceedings of the IEEE, vol. 75, pp. 1235-1245, 1987.
-
(1987)
Proceedings of the IEEE
, vol.75
, pp. 1235-1245
-
-
Lee, E.A.1
Messerschmidt, D.G.2
-
30
-
-
0029309183
-
Dataflow process networks
-
Lee, E. A. and T. M. Parks. Dataflow Process Networks, Proceedings of the IEEE, vol. 83, no. 5. pp. 773-799, 1995.
-
(1995)
Proceedings of the IEEE
, vol.83
, Issue.5
, pp. 773-799
-
-
Lee, E.A.1
Parks, T.M.2
-
31
-
-
0034262309
-
Prophid: A platform-based design method
-
Leijten, J. A. J., J. L. van Meerbergen, A. H. Timmer, and J. A. G. Jess. Prophid: A Platform-Based Design Method, Journal of Design Automation for Embedded Systems, vol. 6, no. 1, pp. 5-37, 2000.
-
(2000)
Journal of Design Automation for Embedded Systems
, vol.6
, Issue.1
, pp. 5-37
-
-
Leijten, J.A.J.1
Van Meerbergen, J.L.2
Timmer, A.H.3
Jess, J.A.G.4
-
32
-
-
0034854046
-
Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip
-
Lyonnard, D., S. Yoo, A. Baghdadi, and A. A. Jerraya. Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. In Proceedings of the Design Automation Conference, pp. 518-523, 2001.
-
(2001)
Proceedings of the Design Automation Conference
, pp. 518-523
-
-
Lyonnard, D.1
Yoo, S.2
Baghdadi, A.3
Jerraya, A.A.4
-
33
-
-
84976718540
-
Algorithms for scalable synchronization on shared-memory multi-processors
-
Mellor-Crummey, J. M. and M. L. Scott. Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors, ACM Transactions on Computers Systems, vol. 9, pp. 21-65, 1991.
-
(1991)
ACM Transactions on Computers Systems
, vol.9
, pp. 21-65
-
-
Mellor-Crummey, J.M.1
Scott, M.L.2
-
34
-
-
0029181969
-
Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems
-
San Jose, CA
-
Nachtergaele, L., F. Catthoor, F. Balasa, F. Franssen, E. de Greef, H. Samsom, and H. de Man. Optimization of Memory Organization and Hierarchy for Decreased Size and Power in Video and Image Processing Systems. In Proceedings of the International Workshop on Memory Technology, San Jose, CA, 1995.
-
(1995)
Proceedings of the International Workshop on Memory Technology
-
-
Nachtergaele, L.1
Catthoor, F.2
Balasa, F.3
Franssen, F.4
De Greef, E.5
Samsom, H.6
De Man, H.7
-
35
-
-
0031997237
-
System-level power optimization of video coders on embedded cores: A systematic approach
-
Nachtergaele, L., D. Molenaar, B. Vanhoof, F. Catthoor, and H. de Man. System-Level Power Optimization of Video Coders on Embedded Cores: A Systematic Approach. In Journal of VLSI Signal Processing, vol. 18, pp. 89-109, 1998.
-
(1998)
Journal of VLSI Signal Processing
, vol.18
, pp. 89-109
-
-
Nachtergaele, L.1
Molenaar, D.2
Vanhoof, B.3
Catthoor, F.4
De Man, H.5
-
37
-
-
84949958127
-
HWSW co-design and verification of a multistandard video and image codec
-
Peset-Llopis, R., M. Oosterhuis, S. Ramanathan, P. E. R. Lippens, A. van der Werf, S. Maul, and J. Lin. HWSW Co-Design and Verification of a Multistandard Video and Image Codec. In Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 393-398, 2001.
-
(2001)
Proceedings of the IEEE International Symposium on Quality Electronic Design
, pp. 393-398
-
-
Peset-Llopis, R.1
Oosterhuis, M.2
Ramanathan, S.3
Lippens, P.E.R.4
Van Der Werf, A.5
Maul, S.6
Lin, J.7
-
38
-
-
0035509391
-
Platform-based design and software design methodology for embedded systems
-
Sangiovanni-Vincentelli, A. and G. Martin. Platform-Based Design and Software Design Methodology for Embedded Systems, IEEE Design 33, 2001.
-
(2001)
IEEE Design
, vol.33
-
-
Sangiovanni-Vincentelli, A.1
Martin, G.2
-
40
-
-
0034846659
-
Addressing the system-on-a-chip interconnect woesthrough communication-based design
-
M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli. Addressing the System-on-a-Chip Interconnect WoesThrough Communication-Based Design. In Proceedings of Design Automation Conference, pp. 667-672, 2001.
-
(2001)
Proceedings of Design Automation Conference
, pp. 667-672
-
-
Sgroi, M.1
Sheets, M.2
Mihal, A.3
Keutzer, K.4
Malik, S.5
Rabaey, J.6
Sangiovanni-Vincentelli, A.7
-
41
-
-
84944181132
-
Data-reuse and parallel embedded architecures for low-power, real-time multimedia applications
-
Soudris, D., N. Zervas, A. Argyriou, M. Dasygenis, K. Tatas, C. Goutis, and A. Thanailakis. Data-Reuse and Parallel Embedded Architecures for Low-Power, Real-Time Multimedia Applications. In Proceedings of the IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 243-254, 2000.
-
(2000)
Proceedings of the IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation
, pp. 243-254
-
-
Soudris, D.1
Zervas, N.2
Argyriou, A.3
Dasygenis, M.4
Tatas, K.5
Goutis, C.6
Thanailakis, A.7
-
42
-
-
0004141908
-
-
The Netherlands: Prentice Hall International Inc.
-
Tanenbaum, A. S. Computer Networks, The Netherlands: Prentice Hall International Inc., 1981.
-
(1981)
Computer Networks
-
-
Tanenbaum, A.S.1
-
43
-
-
0033901302
-
The koala component model for consumer electronics software
-
van Ommering, R., F. van der Linden, J. Kramer, and J. Magee. The Koala Component Model for Consumer Electronics Software, IEEE Computer, vol 33. pp. 78-85, 2000.
-
(2000)
IEEE Computer
, vol.33
, pp. 78-85
-
-
Van Ommering, R.1
Van Der Linden, F.2
Kramer, J.3
Magee, J.4
-
44
-
-
0030263667
-
CoWare - A design environment for heterogeneous hardware/software systems
-
van Rompaey, K., D. Verkest, I. Bolsens, and H. de Man. CoWare-A Design Environment for Heterogeneous Hardware/Software Systems. In Proceedings of the Design Automation for Embedded Systems Conference, pp. 357-386, 1996.
-
(1996)
Proceedings of the Design Automation for Embedded Systems Conference
, pp. 357-386
-
-
Van Rompaey, K.1
Verkest, D.2
Bolsens, I.3
De Man, H.4
|