A parallel VLSI architecture for layered decoding for array LDPC codes

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 738-743

  Gunnam, Kiran K ^a   Choi, Gwan S ^a   Yeary, Mark B ^b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b UNIVERSITY OF OKLAHOMA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SIZES; DATA REUSING; DECODER ARCHITECTURE; INTERNATIONAL CONFERENCES; LAYERED DECODING; LDPC DECODERS; LOW DENSITY PARITY CHECK (LDPC); MICRON TECHNOLOGY (CO); MIN-SUM; PARALLEL ARCHITECTURES; PUNCTURED LOW DENSITY PARITY CHECK (LDPC) CODES; SIGNIFICANT REDUCTION; STORAGE REQUIREMENTS; VLSI ARCHITECTURES; VLSI DESIGNS; VLSI IMPLEMENTATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CODES (STANDARDS); CODES (SYMBOLS); COMPUTER PROGRAMMING LANGUAGES; DECODING; INTEGRATED CIRCUITS;

EMBEDDED SYSTEMS;

EID: 39349104903     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.19     Document Type: Conference Paper

References (11)

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