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Volumn 5, Issue 1, 2008, Pages 17-22

Quo Vadis nanoelectronics?

Author keywords

[No Author keywords available]

Indexed keywords

(2+1) DIMENSIONS; (E ,3E) PROCESS; (MIN ,MAX ,+) FUNCTIONS; (OTDR) TECHNOLOGY; CHIP ARCHITECTURE; CHIP SIZES; CIRCUIT ARCHITECTURES; COST PER UNIT; DRIVING FORCES; FINFETS; INTERNATIONAL CONFERENCES; MOORE'S LAWS; NANOWIRE FABRICATION; NEW APPROACHES; NEW DEVICES; NEW TECHNOLOGIES; NONEQUILIBRIUM CARRIER DYNAMICS; NOVEL DEVICES; PROCESSING TECHNOLOGIES; QUANTUM WIRES; ROAD MAPS; SI CMOS; SI DEVICES; TECHNOLOGICAL FACTORS; VERTICAL QUANTUM WIRES;

EID: 38849160105     PISSN: 18626351     EISSN: None     Source Type: Journal    
DOI: 10.1002/pssc.200776580     Document Type: Conference Paper
Times cited : (5)

References (29)
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    • M. Lundstrom, Z. Ren, and S. Datta, 2000 SISPAD Tech. Dig., pp. 1-5, 2000.
    • M. Lundstrom, Z. Ren, and S. Datta, 2000 SISPAD Tech. Dig., pp. 1-5, 2000.
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    • 33744527528 scopus 로고    scopus 로고
    • R. Akis, M. J. Gilbert, and D. K. Ferry, J. Phys. Conf. Series 38, 87 (2006).
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  • 13
    • 0141642013 scopus 로고    scopus 로고
    • See, e.g
    • See, e.g., L. Samuelson, Mater. Today 6(10), 22 (2003).
    • (2003) Mater. Today , vol.6 , Issue.10 , pp. 22
    • Samuelson, L.1
  • 16
    • 27144474479 scopus 로고    scopus 로고
    • R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar, and M. Radosavljevic, 2005 IEEE VLSI-TSA Int. Symp. Tech. Dig., pp. 13-16, 2005.
    • R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar, and M. Radosavljevic, 2005 IEEE VLSI-TSA Int. Symp. Tech. Dig., pp. 13-16, 2005.
  • 20
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    • A. Bertoni, R. Ionicioiu, P. Zanardi, F. Rossi, and C. Jacoboni, Physica B: Cond. Matter 314, 10 (2002).
    • A. Bertoni, R. Ionicioiu, P. Zanardi, F. Rossi, and C. Jacoboni, Physica B: Cond. Matter 314, 10 (2002).


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.