On silicon-based speed path identification

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 35-41

  Lee, Leonard ^a   Wang, Li C ^a   Parvathala, Praveen ^b   Mak, T M ^b  

^a University of California   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH-PERFORMANCE DESIGN; PATH IDENTIFICATIONS; PRODUCTION TEST; SILICON DEBUG; SILICON SAMPLES; SPEED BINNING; SPEED LIMITING PATHS; TIMING INFORMATION;

ITERATIVE METHODS; SPEED;

SILICON;

EID: 84886581451     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.61     Document Type: Conference Paper

References (8)

1. Angela Krstic, et. al. Delay Defect Diagnosis Based Upon Statistical Timing Models-The First Step. in Proc. DATE, 2003, pp. 328-323
2. Agarwal, A.; Dartu, F.; Blaauw, D. Statistical gate delay model considering multiple input switching in Proc. DAC, 2004 pp. 658-663
3. Cory, B. D.; Kapur, R.; Underwood, B. Speed binning with path delay test in 150-nm technology. IEEE D&T, Vol 20, No 5, 2003, pp. 41-45
4. Leonard Lee, Li-C. Wang, T. M. Mak, and Kwang-Ting Cheng. A Path-Based Methodology for Post-Silicon Timing Validation. in Proc. ICCAD, 2004.
5. Li-C. Wang. Regression Simulation: applying path-based learning in delay test and post-silicon validation in Proc. DATE, March 2004, pp. 692-693.
6. Li-C. Wang, et. al. On Path-based Learning and Its Applications in Delay Test and Diagnosis in Proc. ACM/IEEE DAC, June 2004
7. Kai Yang, et. al. TranGen: A SAT-Based ATPG for Path-Oriented Transition Faults. in Proc. ASP-DAC, Jan 2004.
8. Anacad. Eldo v4. 4. x User's Manual. 1996