Theoretical studies on metal/high-k gate stacks

ECS Transactions

Volumn 6, Issue 1, 2007, Pages 191-204

  Shiraishi, Kenji ^a,b   Akasaka, Yasushi ^a,c,i   Nakamura, Genji ^c,i   Nakayama, Takashi ^d   Miyazaki, Seiichi ^e   Watanabe, Heiji ^f   Ohta, Akio ^e   Ohmori, Kenji ^g   Chikyow, Toyohiro ^g   Nara, Yasuo ^c   Yamabe, Kikuo ^a   Yamada, Keisaku ^h  

^a UNIVERSITY OF TSUKUBA   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

^c SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^d CHIBA UNIVERSITY   (Japan)

^e HIROSHIMA UNIVERSITY   (Japan)

^f OSAKA UNIVERSITY   (Japan)

^g NATIONAL INSTITUTE FOR MATERIALS SCIENCE   (Japan)

^h WASEDA UNIVERSITY   (Japan)

ⁱ TOKYO ELECTRON LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; FERMI LEVEL; HIGH-K DIELECTRIC; LOGIC GATES; METALS; TEMPERATURE; WAVE FUNCTIONS; WORK FUNCTION;

AFTER HIGH TEMPERATURE; EFFECTIVE WORK FUNCTION; ELECTRON TRANSFER; FERMI LEVEL PINNING; INTERFACE STRUCTURES; LOW TEMPERATURE TREATMENT; SI SUBSTRATES; THEORETICAL STUDY;

GATE DIELECTRICS;

EID: 37749039000     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2727402     Document Type: Conference Paper

References (24)

1. G. D. Wilk and R. M. Wallace, Appl. Phys. Lett, 74, 2854 (1999).
2. G. D. Wilk, R. M. Wallace, J. M. Anthony, J. Appl. Phys., 89, 5243 (2001).
3. Y. Akasaka, G. Nakamura, K. Shiraishi, N. Umezawa, K. Yamabe, O. Ogawa, M-B Lee, T. Amiaka, T. Kasuya, H. Watanabe, T. Chikyow, F. Ootsuka, Y. Nara and K. Nakamura., Jpn. J Appl. Phys. 45, L1289 (2006).
4. R. Jha, B. Lee, B. Chen, S. Novak, P. Majhi and V. Misra, p.47, Technical Digest of IEEE International Electron Devices Meeting, Washington DC, USA, (2005).
5. M. Koyama, Y. Kamimuta, T. Ino, A. Kaneko, S. Inumiya, K. Eguchi, M. Takayanagi, and A. Nishiyama., p.499, Technical Digest of IEEE International Electron Devices Meeting, San Francisco, USA, (2004).
6. C Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, P. Tobin, p.9, Technical Digest of 2003 Symposium on VLSI Technology, Kyoto, Japan, (2003).
7. J. Tersoff, Phys. Rev. Lett., 52, 465 (1984).
8. M. Cardona and N. E. Christensen. Phys. Rev. B, 35, 6182 (1987).
9. J. Robertson, J Vac. Sci. Technol. B, 18, 1785 (2000).
10. K. Shiraishi, K. Yamada, K. Torii, Y. Akasaka, K. Nakajima, M. Konno, T. Chikyo, H. Kitajima, T. Arikado, p.108, Technical Digest of 2004 Symposium on VLSI Technology, Honolulu, USA, (2004).
11. K. Shiraishi, K. Yamada, K. Torii, Y. Akasaka, K. Nakajima, M. Konno, T. Chikyo, H. Kitajima, and T. Arikado, Jpn. J Appl. Phys. Part 2, 43, L1413 (2004).
12. K. Shiraishi, K. Yamada, K. Torii, Y. Akasaka, K. Nakajima, M. Konno, T. Chikyo, H. Kitajima, T. Arikado, and Y. Nara, Thin Solid Films, 508, 305 (2006).
13. K. Shiraishi, K. Torii, Y. Akasaka, T. Nakayama, T. Nakaoka, S. Miyazaki, T. Chikyow, K. Yamada, and Y. Nara, ECS Transactions, 1 (5) 479 (2006).
14. E. Cartier, F.R. McFeely, V. Narayanan, P. Jamison, B. P. Linder, M. Copel, V. K. Pruchuri, V. S. Basker, R. Haight, D. Lim, R. Carruthers, T. Shaw, M. Steen, J. Sleight, J. Rubino, H. Deligianni, S. Guha, R. Jammy and G. Shahidi, p.230, Tech. Digest of 2005 Symposium on VLSI Technology, Kyoto, Japan, (2005).
15. Y. Kamimuta, M. Koyama, T. Ino, K. Sekine, M. Sato, K. Eguchi, M. Takayanagi, M. Tomita, and A. Nishiyama, p.24, Extended Abstracts of the 2005 Conference on Solid State Device and Materials, Kobe, Japan, (2005).
16. M. Takayanagi, T. Watanabe, R. Iijima, A. Kaneko, S. Inumiya, I. Hirano, K. Sekine, A. Nishiyama, K. Eguchi, Y. Tsunashima, p.174, Extended Abstracts of International Workshop on Gate Insulator, Tokyo, Japan, (2003).
17. L. Pantisano, P. J. Chen, V. Afanas'ev, L-A, Ragnarsson, G.. Pourtois, G. Groeseneken, p. 122, Technical Digest of 2004 Symposium on VLSI Technology, Honolulu, USA, June (2004).
18. H. Takeuchi, D. Ha, T-J. King, J Vac. Sci. Technol A, 22, 1337 (2004).
19. A. Filippetti, V. Fiorentini, and G. M. Lopez, ECS Transaction, 3 (3) 267 (2006).
20. M. Ikeda, G. Kresse, M. Kadoshima, T. Nabatame, H. Satake, and A. Toriumi, p.222, Extended Abstracts of the 2006 Conference on Solid State Device and Materials, Yokohama, Japan, (2006).
21. A. Ohta, S. Miyazaki, Y. Akasaka, H. Watanabe, K. Shiraishi, K. Yamada, S. Inumiya, and Y. Nara, p.61, Extended Abstracts of 2006 International Workshop on Dielectric Thin Films for Future ULSI Devices - Science and Technology, Kawasaki, Japan, (2006).
22. K. Shiraishi, Y. Akasaka, S. Miyazaki, T. Nakayama, T. Nakaoka, G. Nakamura, K. Torii, H. Furutou, A. Ohta, P. Ahmet, K. Ohmori, H. Watanabe, T. Chikyow, M. L. Green, Y. Nara, and K. Yamada, p.43, Technical Digest of IEEE International Electron Devices Meeting, Washington D.C, USA, (2004).
23. K. Shiraishi, T. Nakayama, Y. Akasaka, S. Miyazaki, T. Nakaoka, K. Ohmori, P. Ahmet, K. Torii, H. Watanabe, T. Chikyow, Y. Nara, H. Iwai, and K. Yamada, ECS Transactions, 2 (1) 25 (2006).
24. T. Nakayama, K. Shiraishi, S. Miyazaki, Y. Akasaka, T. Nakaoka, K. Torii, A. Ohta, P. Ahmet, K. Ohmori, N. Umezawa, H. Watanabe, T. Chikyow, Y. Nara, H. Iwai, and K. Yamada, ECS Transactions, 3 (3) 129-140 (2006).