Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 255-260

  Babu, Hafiz Md Hasan ^a   Chowdhury, Ahsan Raja ^a  

^a UNIVERSITY OF DHAKA   (Bangladesh)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY CODES; ERROR CORRECTION; GATES (TRANSISTOR); NUMBER THEORY;

ADDER CIRCUIT; BINARY CODED DECIMAL (BCD) ADDER; BINARY VARIABLES;

ADDERS;

EID: 27944471818     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. Bennett, C., "Logical Reversibility of Computation," IBM Journal of Research and Development, 17, 1973, 525-532.
2. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury, "Reversible Logic Synthesis for Minimization of Full-adder Circuit", IEEE Conference on Digital System Design 2003, Euro-Micro'03, Belek, Antalya, Turkey, 2003, pp. 50-54.
3. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury, "Synthesis of Full-adder Circuit Using Reversible Logic", 17th International Conference on VLSI design 2004, Mumbai, India, 2004, pp. 757-760.
4. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury, "On the Realization of Reversible Full-Adder Circuit", International Conference on Computer and Information Technology, Dhaka, Bangladesh, 2003, Vol. 2, pp. 880-883.
5. Ronald J. Tocci, Digital Systems- Principles and Application, New Delhi, India, 1996.
6. R. Landauer, "Irreversibility and Heat Generation in the Computational Process", IBM Journal of Research Development, 5 ,1961, 183-191.
7. Md. M. H Azad Khan, "Design of Full-adder With Reversible Gates", International Conference on Computer and Information Technology, Dhaka, Bangladesh, 2002, pp. 515-519.
8. E. Fredkin, T. Toffoli, "Conservative Logic", International Journal of Theor. Physics, 21, 1982, pp. 219-253.
9. Milburn, Gerard J., The Feynman Processor, Perseus Books, 1998.
10. R. Feynman, "Quantum Mechanical Computers", Optical News, 1985, pp. 11-20.
11. T. Toffoli., "Reversible Computing", Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980).
12. P.D. Picton, "Fredkin Gates as the Basic for Comparison of Different Logic Designs", Synthesis and Optimization of Logic Systems, London, UK, 1994.
13. M. Perkowski, L. Jozwiak, P. Kerntopf, A Mishchenko, A. Al-Rabadi, A. Coppola, A. Buller, X Song, M. M. H. A. Khan, S Yanushkevich, V.S Shmerko, and M. Chzazowska-Jeske, "A general decomposition for reversible logic", in: Proc. RM'01.
14. Andrel B. Khlopotine, M Perkowski and Pawel Kerntopf, "Reversible Logic Synthesis by Iterative Composition", in: Proc. IWLS '02,pp. 261-266.
15. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Hoque, Ahsan Raja Chowdhury, "Logic Synthesis and Minimization of Boolean Functions Using TANT Network", International conference on computer and information technology 2003, 19-21, Dhaka, Bangladesh, Dec 2003, Vol-2 pp.884-889.
16. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Hoque, Ahsan Raja Chowdhury, "Heuristic approach to synthesize Boolean functions using TANT network", IEEE, International Symposium on Circuits and Systems, Vancouver, Canada, 23-26 May 2004, VLSI-L7.4, vol. II, pp. 373 - 376.