Reversible logic synthesis for minimization of full-adder circuit

Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

Volumn , Issue , 2003, Pages 50-54

  Babu, Hafiz Md Hasan ^a   Islam, Md Rafiqul ^a   Chowdhury, Ahsan Raja ^a   Chowdhury, Syed Mostahed Ali ^a  

^a UNIVERSITY OF DHAKA   (Bangladesh)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER CIRCUITS; LOGIC CIRCUITS; LOGIC GATES; SYSTEMS ANALYSIS; TIMING CIRCUITS;

FUTURE TECHNOLOGIES; GARBAGE OUTPUT; NUMBER OF GATES; OUTPUT VECTORS; REVERSIBLE CIRCUITS; REVERSIBLE GATES; REVERSIBLE LOGIC; REVERSIBLE LOGIC SYNTHESIS;

LOGIC SYNTHESIS;

ALGORITHMS; ELECTRIC CIRCUITS; FUZZY LOGIC;

EID: 84944327186     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2003.1231899     Document Type: Conference Paper

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