메뉴 건너뛰기




Volumn 2006, Issue , 2006, Pages 387-392

Novel BCD adders and their reversible logic implementation for IEEE 754r format

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); NANOTECHNOLOGY; OPTICAL DATA PROCESSING;

EID: 33748528595     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2006.122     Document Type: Conference Paper
Times cited : (58)

References (19)
  • 2
    • 33748527855 scopus 로고    scopus 로고
    • http://en.wikipedia.org/wiki/IEEE_754r
  • 3
    • 33748568847 scopus 로고    scopus 로고
    • http://www2.hursley.ibm.com/decimal/754r-status.html
  • 4
    • 0000328287 scopus 로고
    • Irreversibility and heat generation in the computational process
    • R. Landauer, "Irreversibility and Heat Generation in the Computational Process", IBM Journal of Research and Development, 5, pp. 183-191, 1961.
    • (1961) IBM Journal of Research and Development , vol.5 , pp. 183-191
    • Landauer, R.1
  • 5
    • 0015680909 scopus 로고
    • Logical reversibility of computation
    • November
    • C.H. Bennett, "Logical Reversibility of Computation", IBM J. Research and Development, pp. 525-532, November 1973.
    • (1973) IBM J. Research and Development , pp. 525-532
    • Bennett, C.H.1
  • 7
    • 0004245012 scopus 로고
    • Reversible computing
    • MIT Lab for Computer Science
    • T. Toffoli., "Reversible Computing", Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980).
    • (1980) Tech Memo , vol.MIT-LCS-TM-151
    • Toffoli, T.1
  • 8
    • 23844558805 scopus 로고    scopus 로고
    • Simulating the fredkin gate with energy{Based P systems
    • Alberto LEPORATI, Claudio ZANDRON, Giancarlo MAURI," Simulating the Fredkin Gate with Energy{Based P Systems", Journal of Universal Computer Science,Volume 10,Issue 5,pp 600-619.
    • Journal of Universal Computer Science , vol.10 , Issue.5 , pp. 600-619
    • Leporati, A.1    Zandron, C.2    Mauri, G.3
  • 11
    • 27944471818 scopus 로고    scopus 로고
    • Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder
    • Kolkata, India, Jan
    • Hafiz Md. Hasan Babu and Ahsan Raja Chowdhury,"Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-bit Parallel Adder",VLSI Design 2005,pp-255-260,Kolkata, India, Jan 2005.
    • (2005) VLSI Design 2005 , pp. 255-260
    • Babu, H.Md.H.1    Chowdhury, A.R.2
  • 12
    • 33845188112 scopus 로고    scopus 로고
    • A novel reversible TSG gate and its application for designing reversible carry look-ahead and other adder architectures
    • Accepted in Singapore, October 24-26
    • Himanshu Thapliyal and M.B Srinivas, "A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures", Accepted in Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC05), Singapore, October 24-26, 2005
    • (2005) Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC05)
    • Thapliyal, H.1    Srinivas, M.B.2
  • 19
    • 20444493667 scopus 로고    scopus 로고
    • PhD Dissertion, Computer Science Department, University of New Brunswick, Canada, Oct
    • Dmitri Maslov, "Reversible Logic Synthesis" ,PhD Dissertion, Computer Science Department, University of New Brunswick, Canada, Oct 2003.
    • (2003) Reversible Logic Synthesis
    • Maslov, D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.