Online testable reversible logic circuit design using NAND blocks

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2004, Pages 324-331

  Vasudevan, D P ^a   Lala, P K ^a   Parkerson, J P ^a  

^a University of Arkansas   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUITS; COMPLEXITY LEVELS; SUBSETS;

BENCHMARKING; SET THEORY;

LOGIC CIRCUITS;

EID: 24944558180     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2004.1347856     Document Type: Conference Paper

References (9)

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2. C. H. Bennett, 'Logical Reversibility of Computation", IBM J. Research and Development, pp. 525-532, November 1973.
3. M Perkowski and P Kerntopf, 'Reversible Logic", invited tutorial, Proc, EURO -MICRO, Warsaw, Poland, Sept 2001.
4. E. Fredkin and T. Toffoli, "Conservative Logic", Intl. J. Theoretical Physics, vol. 21, nos.3 -4, pp. 219-253, 1982.
5. T.Sasao and K. Kinoshita, "Conservative Logic Elements and Their Universality", IEEE Trans. Computers, vol. 28, no. 9, pp. 682-685, 1979.
6. Abhinav Agrawal and Niraj K. Jha, "Reversible Logic Synthesis," in Proc. IEEE Design Automation & Test in Europe Conf, Feb. 2004
7. V.V.Shende, A.K.Prasad, I.L.Markov, and J.P.Hayes, "Reversible logic circuit synthesis," in Proc. Int. Conf. Computer-Aided Design, Nov.2003, pp. 125-132.
8. D.M.Miller, D.Maslov, and G.W. Dueck," A transformation based algorithm for reversible logic synthesis,"in Proc.Design Automation Conf., June 2003.
9. Parag K. Lala, Self-checking and Fault Tolerant Digital Design, Morgan Kaufmann, 2001.