A constant-mobility method to enable MOSFET series-resistance extraction

IEEE Electron Device Letters

Volumn 28, Issue 12, 2007, Pages 1132-1134

  Lin, Da Wen ^a,b   Cheng, Ming Lung ^a   Wang, Shyg Wei ^a   Wu, Chung Cheng ^a   Chen, Ming Jer ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Mobility; MOSFET; Series resistance

Indexed keywords

BIAS CURRENTS; CARRIER MOBILITY; ELECTRIC FIELD EFFECTS;

GATE-OXIDE THICKNESS; SERIES RESISTANCE; SHORT-CHANNEL DEVICES;

MOSFET DEVICES;

EID: 36549017106     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.909850     Document Type: Article

References (17)

1. J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho, "A new method to determine MOSFET channel length," IEEE Electron Device Lett., vol. EDL-1, no. 9, pp. 170-173, Sep. 1980.
2. B. J. Sheu, C. Hu, P. K. Ko, and F.-C. Hsu, "Source-and-drain series resistance of LDD MOSFETs," IEEE Electron Device Lett., vol. EDL-5, no. 9, pp. 365-367, Sep. 1984.
3. Y. Taut, D. S. Zicherman, D. R. Lombardi, P. J. Restle, C. H. Hsu, H. I. Hanafi, M. R. Wordeman, B. Davari, and G. G. Shahidi, "A new "shift and ratio" method for MOSFET channel-length extraction," IEEE Electron Device Lett., vol. 13, no. 5, pp. 267-269, May 1992.
4. Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, and C. H. Diaz, "Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs," IEEE Trans. Electron Devices vol. 52, no. 1, pp. 30-38, Jan. 2005.
5. J. C. Guo, S. S. Chung, and C. H. Hsu, "A new approach to determine the effective channel length and drain-to-source series resistance of miniaturized MOSFETs," IEEE Trans. Electron Devices, vol. 41, no. 10, pp. 1811-1818, Oct. 1994.
6. K. Chen, H. C. Wann, J. Dunster, P. K. Ko, and C. Hu, "MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages," Solid State Electron., vol. 39, no. 10, pp. 1515-1518, Oct. 1996.
7. S. Matsumoto, K. Hisamitsu, M. Tanaka, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka, and N. Nakayama, "Validity of mobility universality for scaled metal-oxide-semiconductor field-effect transistors down to 100 nm gate length," J. Appl. Phys. vol. 92, no. 9, pp. 5228-5232, Nov. 2002.
8. A. G. Sabnis and J. T. Clemens, "Characterization of the electron mobility in the inverted (100) Si surface," in IEDM Tech. Dig., 1979, pp. 18-21.
9. S. C. Sun and J. D. Plummer, "Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces," IEEE Trans. Electron Devices, vol. ED-27, no. 8, pp. 1497-1508, Aug. 1980.
10. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFETs: Part I - Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357-2362, Dec. 1994.
11. B. Cheng and J. Woo, "A temperature-dependent MOSFET inversion layer carrier mobility model for device and circuit simulation," IEEE Trans. Electron Devices, vol. 44, no. 2, pp. 343-345, Feb. 1997.
12. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge University Press, 1998, ch. 3.
13. C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M.-S. Liang, "Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65 nm high-performance strained-Si device application," in VLSI Symp. Tech. Dig., 2004, pp. 56-57.
14. W. P. N. Chen, P. Su, J. S. Wang, C. H. Lien, C. H. Chang, K. Goto, and C. H. Diaz, "A new series resistance and mobility extraction method by BSIM model for nano-scale MOSFETs." in Proc. Symp. VLSI-TSA, 2006, pp. 143-144.
15. J. R. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Trans. Electron Devices, vol. 43, no. 11, pp. 1981-1988, Nov. 1996.
16. N. B. Lukyanchikova, M. V. Petrichuk, N. P. Garbar, E. Simoen, and C. Claeys, "Influence of the substrate voltage on the random telegraph signal parameters in submicron n-channel metal-oxide-semiconductor field-effect transistors under a constant inversion charge density," Appl. Phys. A, Solids Surf., vol. 70, no. 3, pp. 345-353, 2000.
17. 2 interface trap modeling," Solid State Electron., vol. 35, no. 6, pp. 843-854, Jun. 1992.