Reduction of gate-to-channel tunneling current in FinFET structures

Solid-State Electronics

Volumn 51, Issue 11-12, 2007, Pages 1466-1472

  Rudenko, T ^a   Kilchytska, V ^b   Collaert, N ^c   Jurczak, M ^c   Nazarov, A ^a   Flandre, D ^b  

^a INSTITUTE OF SEMICONDUCTOR PHYSICS   (Ukraine)

^b UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^c IMEC   (Belgium)

Author keywords

Double gate silicon on insulator MOSFET; FinFET; Gate tunneling current; Multi gate FETs

Indexed keywords

ELECTRIC CURRENTS; LEAKAGE CURRENTS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; THICKNESS MEASUREMENT;

GATE TUNNELING CURRENT; OXIDE THICKNESS; QUASI PLANAR STRUCTURES;

GATES (TRANSISTOR);

EID: 36349015289     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.09.016     Document Type: Article

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