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Volumn 2, Issue , 2005, Pages 1098-1101

Timing analysis considering temporal supply voltage fluctuation

Author keywords

[No Author keywords available]

Indexed keywords

TIMING CIRCUITS;

EID: 33646254740     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120833     Document Type: Conference Paper
Times cited : (34)

References (10)
  • 1
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    • Power and ground network topology optimization for cell based VLSIs
    • T, Mitsuhashi and E. S. Kuh, 'Power and Ground Network Topology Optimization for Cell Based VLSIs,"Proc. DAC, pp.524-529, 1992.
    • (1992) Proc. DAC , pp. 524-529
    • Mitsuhashi, T.1    Kuh, E.S.2
  • 2
    • 0028731948 scopus 로고
    • Decoupling capacitor calculations for CMOS circuits
    • L. Smith, 'Decoupling Capacitor Calculations for CMOS Circuits," Proc. F.PEP, pp.101-105, 1994.
    • (1994) Proc. F.PEP , pp. 101-105
    • Smith, L.1
  • 3
    • 0034474847 scopus 로고    scopus 로고
    • Path selection and pattern generation for dynamic timing analysis considering power supply noise effects
    • J.-J. Liou, A, Krstic, Y.-M. Jiang and K.-T. Cheng, 'Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects," Proc. ICCAD, pp. 493-496, 2000.
    • (2000) Proc. ICCAD , pp. 493-496
    • Liou, J.-J.1    Krstic, A.2    Jiang, Y.-M.3    Cheng, K.-T.4
  • 4
    • 0034846652 scopus 로고    scopus 로고
    • Static timing analysis includeing power supply noise effect on propagation delay in VLSI circuits
    • G. Bai, S. Bobba and I. N. Hajj, 'Static Timing Analysis Inciudeing Power Supply Noise Effect on Propagation Delay in VLSI Circuits," Proc. QAC,2001.
    • (2001) Proc. QAC
    • Bai, G.1    Bobba, S.2    Hajj, I.N.3
  • 5
    • 0036045515 scopus 로고    scopus 로고
    • Coping with buffer delay change due to power and ground noise
    • L. H. Chen, M. Marek-Sadowska and E Brewer, 'Coping with Buffer Delay Change due to Power and Ground Noise," Proc. DAC, pp. 860865, 2002.
    • (2002) Proc. DAC , pp. 860-865
    • Chen, L.H.1    Marek-Sadowska, M.2    Brewer, E.3
  • 6
    • 0348040159 scopus 로고    scopus 로고
    • Vectorless analysis of supply noise induced delay variation
    • S. Pant, D. Blaauw, V, Zolotov, S. Sundareswaran and R. Panda, "Vectorless Analysis of Supply Noise Induced Delay Variation," Proc. IC CAD, pp.184-f91, 2003.
    • (2003) Proc. IC CAD , pp. 184-191
    • Pant, S.1    Blaauw, V.D.2    Sundareswaran, Z.S.3    Panda, R.4
  • 7
    • 0348040157 scopus 로고    scopus 로고
    • Timing analysis in presence of power supply and ground voltage variations
    • R. Ahmadi and F. N. Najm, 'Timing Analysis in Presence of Power Supply and Ground Voltage Variations," Proc. ICCAD, pp.176-183, 2003.
    • (2003) Proc. ICCAD , pp. 176-183
    • Ahmadi, R.1    Najm, F.N.2
  • 8
    • 84861449683 scopus 로고    scopus 로고
    • Timing analysis considering spatial power/ground level variation
    • to appear
    • M. Hashimoto, J. Yamaguchi and H. Onodera, 'Timing Analysis Considering Spatial Power/Ground Level Variation," Proc. ICCAD, to appear.
    • Proc. ICCAD
    • Hashimoto, M.1    Yamaguchi, J.2    Onodera, H.3
  • 9
    • 2442482721 scopus 로고    scopus 로고
    • Impact of power-supply noise on timing in high-frequency microprocessors
    • Feb.
    • M. Saint-Laurent and M. Swaminathan, 'Impact of Power-Supply Noise on Timing in High-Frequency Microprocessors," IEEE Tram. Advanced Packaging, Vol. 27, No. 1, Feb. 2004.
    • (2004) IEEE Tram. Advanced Packaging , vol.27 , Issue.1
    • Saint-Laurent, M.1    Swaminathan, M.2
  • 10
    • 2442653861 scopus 로고    scopus 로고
    • How scaling will change processor architecture
    • M. Horowitz and W. Dally, 'How Scaling Will Change Processor Architecture "Proc. ISSCC, pp.132-133, 2004.
    • (2004) Proc. ISSCC , pp. 132-133
    • Horowitz, M.1    Dally, W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.