Logical effort of higher valency adders

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2004, Pages 1358-1362

  Harris, David ^a  

^a HARVEY MUDD COLLEGE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; CRITICAL PATH ANALYSIS; LOGIC GATES; MICROPROCESSOR CHIPS; TRANSISTORS; TREES (MATHEMATICS);

DOMINO GATES; HIGHER VALENCY PARALLEL PREFIX ADDERS; LOGICAL EFFORTS (LE); VALENCY GATES;

ADDERS;

EID: 21644478645     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A. Beaumont-Smith and C. Lim, "Parallel prefix adder design," Proc. 15th IEEE Symp. Comp. Arith, pp. 218-225, June 2001.
2. D. Harris and I. Sutherland, "Logical effort of carry propagate adders," Proc. 37th Asilomar Conf. Signals, Systems, and Computers, pp. 673-678, 2003.
3. T. Lynch and E. Swartzlander, "A spanning tree carry lookahead adder," IEEE Trans. Computers, vol. 41, no. 8, Aug. 1992, pp. 931-939.
4. S. Mathew, M. Anders, R. Krishnamurthy, and S. Borkar, "A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core," J. Solid-State Circuit, vol. 38, no. 5, May 2003, pp. 689-695.
5. S. Naffziger, "A subnanosecond 0.5 μm 64b adder design," Intl. Solid-state Circuits Conf., 1996, pp. 362-363.
6. N. Weste and D. Harris, CMOS VLSI Design, Addison-Wesley, 2005.