Feasibility study of logic circuits with a spin wave bus

Nanotechnology

Volumn 18, Issue 46, 2007, Pages

  Khitun, Alexander ^a   Nikonov, Dmitri E ^b   Bao, Mingqiang ^a   Galatsis, Kosmas ^a   Wang, Kang L ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; DATA PROCESSING; LOGIC CIRCUITS; PARAMETER ESTIMATION; TRANSISTORS;

CONVENTIONAL ELECTRONIC TRANSMISSION LINES; INFORMATION CARRIER; SIGNAL ATTENUATION; SIGNAL PHASE VELOCITY;

SPIN WAVES;

METAL;

ARCHITECTURE; ARTICLE; ATTENUATION; COMPARATIVE STUDY; DEVICE; ELECTRICITY; ELECTRONICS; ENERGY; EXPERIMENTAL STUDY; FEASIBILITY STUDY; INFORMATION PROCESSING; LOGIC CIRCUIT; PARAMETER; PRIORITY JOURNAL; QUANTITATIVE STUDY; SEMICONDUCTOR; SIMULATION; SPIN WAVE BUS; THEORETICAL STUDY; VELOCITY;

EID: 36048939801     PISSN: 09574484     EISSN: 13616528     Source Type: Journal    
DOI: 10.1088/0957-4484/18/46/465202     Document Type: Article

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