-
1
-
-
84944389716
-
FoCs-Automatic generation of simulation checkers from formal specifications
-
Proc. of CAV Springer-Verlag
-
Abarbanel Y, Beer I, Gluhovsky L, Keidar S, Wolfsthal Y (2000) FoCs-Automatic generation of simulation checkers from formal specifications. In: Proc. of CAV, vol 1855 of LNCS. Springer-Verlag, pp 538-542
-
(2000)
LNCS
, vol.1855
, pp. 538-542
-
-
Abarbanel, Y.1
Beer, I.2
Gluhovsky, L.3
Keidar, S.4
Wolfsthal, Y.5
-
2
-
-
0025536229
-
A single-state-transition fault model for sequential machines
-
Cheng K-T, Jou J-Y (1990) A single-state-transition fault model for sequential machines. In: Proc. of IEEE ICCAD, pp 226-229
-
(1990)
Proc. of IEEE ICCAD
, pp. 226-229
-
-
Cheng, K.-T.1
Jou, J.-Y.2
-
4
-
-
0029238629
-
Efficient generation of counterexamples and witnesses in symbolic model checking
-
Clarke E, Grumberg O, McMillan K, Zhao X (1995) Efficient generation of counterexamples and witnesses in symbolic model checking. In: Proc. of ACM/IEEE DAC, pp 427-432
-
(1995)
Proc. of ACM/IEEE DAC
, pp. 427-432
-
-
Clarke, E.1
Grumberg, O.2
McMillan, K.3
Zhao, X.4
-
6
-
-
84903211840
-
Coverage metrics for temporal logic model checking
-
Springer New York, NY
-
Chockler H, Kupferman O, Vardi MY (2001) Coverage metrics for temporal logic model checking. In: Proc. of international conference on tools and algorithms for the construction and analysis of systems, vol 2031 of LNCS. Springer, New York, NY, pp 528-542
-
(2001)
Proc. of International Conference on Tools and Algorithms for the Construction and Analysis of Systems, Vol 2031 of LNCS
, pp. 528-542
-
-
Chockler, H.1
Kupferman, O.2
Vardi, M.Y.3
-
7
-
-
0142245458
-
Coverage metrics for formal verification
-
Springer New York, NY
-
Chockler H, Kupferman O, Vardi MY (2003) Coverage metrics for formal verification. In: Correct hardware design and verification methods, vol 2860 of LNCS. Springer, New York, NY, pp 111-125
-
(2003)
Correct Hardware Design and Verification Methods, Vol 2860 of LNCS
, pp. 111-125
-
-
Chockler, H.1
Kupferman, O.2
Vardi, M.Y.3
-
8
-
-
35748944949
-
-
Department of Electrical and Computer Engineering at the University of Texas, Austin Texas97 benchmarks
-
Department of Electrical and Computer Engineering at the University of Texas, Austin (1999) Texas97 benchmarks. In: http://embedded.eecs.berkeley.edu/ research/vis/texas-97
-
(1999)
-
-
-
10
-
-
0022012464
-
Decision procedures and expressiveness in the temporal logic of branching time
-
Emerson E, Halpen J (1985) Decision procedures and expressiveness in the temporal logic of branching time. J Comput Syst Sci 30:1-24
-
(1985)
J Comput Syst Sci
, vol.30
, pp. 1-24
-
-
Emerson, E.1
Halpen, J.2
-
11
-
-
84943637314
-
On the use of a high-level fault model to check properties incompleteness
-
Fedeli A, Fummi F, Pravadelli G, Rossi U, Toto F (2003) On the use of a high-level fault model to check properties incompleteness. In: Proc. of ACM/IEEE MEMOCODE, pp 145-152
-
(2003)
Proc. of ACM/IEEE MEMOCODE
, pp. 145-152
-
-
Fedeli, A.1
Fummi, F.2
Pravadelli, G.3
Rossi, U.4
Toto, F.5
-
13
-
-
79251635413
-
Laerte++: An object oriented high-level TPG for systemC designs.
-
Fin A, Fummi F (2003) Laerte++: an object oriented high-level TPG for systemC designs. In: Languages for system specification: Selected contributions on UML, systemC, system Verilog, mixed-signal systems, and property specification from FDL'03, pp 105-107
-
(2003)
Languages for System Specification: Selected Contributions on UML, SystemC, System Verilog, Mixed-signal Systems, and Property Specification from FDL'03
, pp. 105-107
-
-
Fin, A.1
Fummi, F.2
-
14
-
-
0041521040
-
Fault models and test generation for hardware-software covalidation
-
4
-
Harris I (2003) Fault models and test generation for hardware-software covalidation. IEEE Des Test Comput 20(4):40-47
-
(2003)
IEEE des Test Comput
, vol.20
, pp. 40-47
-
-
Harris, I.1
-
17
-
-
84957035600
-
Have i written enough properties? - A method of comparison between specification and implementation
-
Springer New York, NY
-
Katz S, Grumberg O, Geist D (1999) Have I written enough properties? - A method of comparison between specification and implementation. In: Correct hardware design and verification methods, vol 1703 of LNCS. Springer, New York, NY, pp 280-297
-
(1999)
Correct Hardware Design and Verification Methods, Vol 1703 of LNCS
, pp. 280-297
-
-
Katz, S.1
Grumberg, O.2
Geist, D.3
-
18
-
-
35048865012
-
Mutation coverage estimation for model checking
-
Proc. of international symposium on automated technology for verification and analysis. Springer
-
Lee T-C, Hsiung P-A (2004) Mutation coverage estimation for model checking. In: Proc. of international symposium on automated technology for verification and analysis, vol 3299 of LNCS. Springer, pp 534-368
-
(2004)
LNCS
, vol.3299
, pp. 534-368
-
-
Lee, T.-C.1
Hsiung, P.-A.2
-
19
-
-
0004096622
-
Propositional temporal logics: Decidability and completeness
-
Lichtenstein O, Pnueli A (2000) Propositional temporal logics: decidability and completeness. Log J IGPL 8:55-85
-
(2000)
Log J IGPL
, vol.8
, pp. 55-85
-
-
Lichtenstein, O.1
Pnueli, A.2
-
21
-
-
35748960012
-
-
Politecnico di Torino ITC-99 benchmarks
-
Politecnico di Torino (1999) ITC-99 benchmarks. In: http://www.cad. polito.it/tools/itc99.html
-
(1999)
-
-
-
22
-
-
0035629551
-
An axiomatization of full computation tree logic
-
3
-
Reynolds M (2001) An axiomatization of full computation tree logic. J Symb Log 66(3):1011-1057
-
(2001)
J Symb Log
, vol.66
, pp. 1011-1057
-
-
Reynolds, M.1
-
24
-
-
0035392814
-
Coverage metrics for functional validation of hardware design
-
4
-
Taziran S, Keutzer K (2001) Coverage metrics for functional validation of hardware design. IEEE Des Test Comput 18(4):36-45
-
(2001)
IEEE des Test Comput
, vol.18
, pp. 36-45
-
-
Taziran, S.1
Keutzer, K.2
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