Symbolic functional vector generation for VHDL specifications

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 442-446

  Ferrandi, Fabrizio ^a   Fummi, Franco ^b   Gerli, Luca ^a   Sciuto, Donatella ^a  

^a POLITECNICO DI MILANO   (Italy)

^b UNIVERSITY OF VERONA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CODE REDUNDANCY; FUNCTIONAL CORRECTNESS; FUNCTIONAL TEST; PROCESS INPUTS; STATEMENT COVERAGE; SYMBOLIC ANALYSIS; TIME-CONSUMING TASKS; VECTOR GENERATION;

DESIGN; ERRORS; EXHIBITIONS; REDUNDANCY;

SPECIFICATIONS;

EID: 0003680455     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761163     Document Type: Conference Paper

References (18)

1. K. Barlett, R. Brayton, G. Hachtel, R. Jacoby, R. Rudell, and Sangiovanni-Vincentelli. Don't care set specification in combinational and synchronous logic circuits. IEEE Trans. on CAD/ICAS, 7:723-739, June 1988.
2. C. Bolchini, G. Buonanno, F. Ferrandi, F. Fummi, D. Sci-uto, M. Bombana, P. Cavalloro, and P. Borrego. Defini-tion of methodology for testability analysis at the RTL and CDFG levels requirement specs for functional pattern qual-ity evaluator. Technical Report of Deliverable 2.3.A, Esprit project n.20616-REQUEST, 1996.
3. A. Chandra and V. Iyengar. Constraint solving for test gen-eration: A technique for high-level design verigication. Proc. IEEE ICCD, pages 245-248, 1992.
4. K. Cheng and A. Krishnakumar. Automatic generation of functional vectors using the extended finite state machine model. ACM Trans. on design Automation of Electronic Systems, 1(1):57-59, Jan. 1996.
5. H. Cho, G. Hachtel, S. Jeong, B. Plessier, E. Schwarz, and F. Somenzi. ATPG aspects of FSM verification. Proc. IEEE ICCAD, 1990.
6. D. Corvino, I. Epicoco, F. Ferrandi, F. Fummi, and D. Sci-uto. Automatic VHDL restructuring for RTL synthesis op-timization and testability improvement. Proc. IEEE ICCD, pages 587-596, 1998.
7. O. Coudert, C. Berthet, and J. Madre. Verification of se-quential machines using boolean functions vectors. Proc. Workshop on Applied Formal Methods for Correct VLSI Design, 1989.
8. F. Fallah, S. Devadas, and K. Keutzer. Functional vector generation for HDL models using linear programming and 3-satisfaiability. Proc. ACM/IEEE DAC, pages 528-533, 1998.
9. F. Fallah, S. Devadas, and K. Keutzer. OCCOM: Efficient computation of observability-based code coverage metrics for functional verification. Proc. ACM/IEEE DAC, pages 152-157, 1998.
10. F. Ferrandi, F. Fummi, and D. Sciuto. Implicit test gener-ation for behavioral VHDL models. Proc. IEEE ITC, pages 436-441, 1998.
11. S. Ghosh and T. Chakraborty. On behavior fault modeling for digital designs. Journal of Electronic Testing: Theory and Applications, 2:135-151, 1991.
12. N. Giambiasi, J. Santucci, A. Courbis, and V. Pla. Test pat-tern generation for behavioral descriptions in VHDL. Proc. EuroVHDL, pages 228-235, 1991.
13. R. Grinwald, E. Harel, M. Orgad, S. Ur, and A. Ziv. User defined coverage-a tool supported methodology for design verification. Proc. ACM/IEEE DAC, pages 158-163, 1998.
14. 1991 and 1992 high level synthesis benchmarks. ftp://mcnc.mcnc.org/pub/ benchmark/HLSynth91
15. B. Marick. The craft of software testing. Prentice-Hall, Englewood Clips, pages 221-229, 1995.
16. S. Minato. Generation of BDDs from hardware algorithm descriptions. Proc. IEEE ICCAD, nov 1996.
17. R. Herrmann and H. Pargmann. Computing Binary Deci-sion Diagrams for VHDL Data Types. Proc. European De-sign Automation Conference (EURO-DAC94), pages 578-585, September 1994.
18. T. Riesgo, Y. Torroja, E. De La Torre, and J. Uceda. Qual-ity estimation of test vectors and functional validation pro-cedures based on fault and error models. Proc. IEEE DATE, pages 955-956, 1998.