Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3254, Issue , 2004, Pages 169-178

  Schuster, Christian ^a   Nagel, Jean Luc ^a   Piguet, Christian ^b   Farine, Pierre André ^a  

^a UNIVERSITY OF NEUCHÂTEL   (Switzerland)

^b CSEM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC POWER UTILIZATION;

ARCHITECTURAL LEVELS; ARCHITECTURE COMPARISON; DYNAMIC POWER DISSIPATION; LEAKAGE POWER CONSUMPTION; LEAKAGE REDUCTION; MULTIPLIER ARCHITECTURE; TOTAL POWER CONSUMPTION; VERY DEEP SUB-MICRON TECHNOLOGIES;

LOW POWER ELECTRONICS;

EID: 35048843890     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30205-6_19     Document Type: Article

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