Exploiting instruction level parallelism in processors by caching scheduled groups

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 1997, Pages 13-25

  Nair, Ravi ^a   Hopkins, Martin E ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL LINGUISTICS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; STORAGE ALLOCATION (COMPUTER);

DYNAMIC INSTRUCTION FORMATTING (DIF); VERY LONG INSTRUCTION WORD (VLIW) ARCHITECTURES;

MICROPROCESSOR CHIPS;

EID: 0030674213     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/264107.264125     Document Type: Conference Paper

References (17)