Performance limits of trace caches

Journal of Instruction-Level Parallelism

Volumn 1, Issue , 1999, Pages

  Postiff, Matt ^a   Tyson, Gary ^a   Mudge, Trevor ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FRAGMENTATION; SUPERSCALAR PROCESSORS; TRACE CACHES; ZERO-LATENCY ALIGNMENT NETWORK;

BANDWIDTH; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DECODING; MATHEMATICAL MODELS; OPTIMIZATION; PROGRAM PROCESSORS;

COMPUTER ARCHITECTURE;

EID: 0003230737     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (24)

1. Chih-Po Wen. Improving Instruction Supply Efficiency in Superscalar Architectures Using Instruction Trace Buffers. Proc. Symp. Applied Computing, Volume 1, pp. 28-36, March 1992.
2. S. Melvin, M. Shebanow, and Y. Patt. Hardware support for large atomic units in dynamically scheduled machines. 21st Intl. Symp. on Microarchitecture, pp. 60-63, Dec. 1988.
3. Tse-Yu Yen, Deborah T. Marr and Yale N. Patt. Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache. 1993 Intl. Conf. Supercomputing, pp. 67-76, July 1993.
4. Manoj Franklin and Mark Smotherman. A Fill-Unit Approach to Multiple Instruction Issue. Proc. 27th Intl. Symp. on Microarchitecture, pp. 162-171, Nov. 1994.
5. Mark Smotherman and Manoj Franklin. Improving CISC Instruction Decoding Performance Using a Fill Unit. Proc. 28th Intl. Symp. Microarchitecture, pp. 219-229, Nov. 1995.
6. Alexander Peleg and Uri Weiser. Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line. United States Patent 5,381,533, Jan. 10,1995. http://www.patents.ibm.com/.
7. T. Conte, K. Menezes, P. Mills, and B. Patel. Optimization of instruction fetch mechanisms for high issue rates. 22nd Intl. Symp. On Computer Architecture, pp. 333-344, June 1995.
8. Eric Rotenberg, Steve Bennett and Jim Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. University of Wisconsin, Madison Tech. Report. April, 1996.
9. Eric Rotenberg, Steve Bennett and James E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. Proc. of the 29th Intl. Symp. on Microarchitecture, pp. 24-34, Dec. 1996.
10. Sanjay Jeram Patel, Daniel Holmes Friendly and Yale N. Patt. Critical Issues Regarding the Trace Cache Fetch Mechanism. Computer Science and Engineering, University of Michigan Tech. Report. May 1997.
11. Daniel Holmes Friendly, Sanjay Jeram Patel and Yale N. Patt. Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. Proc. 30th Intl. Symp. Microarchitecture, pp. 24-33, Dec. 1997.
12. Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides and Jim Smith. Trace Processors. Proc. 30th Intl. Symp. Microarchitecture, pp. 138-148, Dec. 1997.
13. Eric Rotenberg, Steve Bennett and James E. Smith. A Trace Cache Microarchitecture and Evaluation. IEEE Transactions on Computers, Vol. 48, No. 2, pp. 111-120. February 1999.
14. Douglas C. Burger and Todd M. Austin. The SimpleScalar Tool Set, Version 2.0. University of Wisconsin, Madison Tech. Report. June 1997.
15. Sanjay J. Patel, Marius Evers and Yale N. Patt. Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. Proc. 25th Intl. Symp. Computer Architecture, pp. 262-271, June 1998.
16. Eric Hao, Po-Yung Chang and Yale N. Patt. The Effect of Speculatively Updating Branch History on Branch Prediction Accuracy, Revisited. Proc. 27th Intl. Symp. Microarchitecture, pp. 228-232, Nov, 1994.
17. Sanjay J. Patel. Delivering Instruction Bandwidth using a Trace Cache. Ph.D. Dissertation. University of Michigan, 1999.
18. Q. Jacobson, E. Rotenberg, and J. Smith. Path-based Next Trace Prediction. 30th Intl. Symp. Microarchitecture, Dec. 1997.
19. Srilatha Manne, Artur Klauser and Dirk Grunwald. Pipeline Gating: Speculation Control For Energy Reduction. Proc. 25th Intl. Symp. Computer Architecture, pp. 132-141, June 1998.
20. T. Sato. NCB: A mechanism for improving instruction fetching efficiency. Proc. 9th Joint Symp. on Parallel Processing, pp. 221-228, May 1997.
21. Alex Ramirez, Josep Ll. Larriba-Pey, Carlos Navarro, Josep Torrellas, and Mateo Valero. Software trace cache. Proc. 13th Intl. Conf. on Supercomputing, pp. 119-126, June 1999.
22. Wen-mei W. Hwu, Scott A. Mahlke, William Y. Chen, Pohua P. Chang, Nancy J. Warter, Roger A. Bringmann, Roland G. Ouellette, Richard E. Hank, Tokuzo Kiyohara, Grant E. Haab, J. G. Holm and D. M. Lavery. The Superblock: An Effective Technique for VLIW and Superscalar Compilation. The Journal Supercomputing, Vol. 7 No. 1-2, pp. 229-248. May 1993.
23. J. A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions on Computers, Vol. C-30 No. 7, pp 478-490, July 1981.
24. P. Y. Hsu and E. S. Davidson. Highly concurrent scalar processing. Proc. 18th Intl. Symp. Computer Architecture, pp. 386-395, June 1986.