DAG based library-free technology mapping

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 293-298

  Marques, F S ^a   Rosa Jr , L S ^a   Ribas, R P ^a   Sapatnekar, S S ^b   Reis, A I ^a,c  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b UNIVERSITY OF MINNESOTA   (United States)

^c Nangate Inc   (United States)

Author keywords

Library free synthesis; Logic synthesis; Switching theory; Technology mapping; Virtual libraries

Indexed keywords

BOOLEAN FUNCTIONS; CONFORMAL MAPPING; GRAPH THEORY; SWITCHING THEORY; TRANSISTORS; VIRTUAL REALITY;

DIRECTED ACYCLIC GRAPH (DAG); LIBRARY FREE SYNTHESIS; LOGIC SYNTHESIS; TECHNOLOGY MAPPING; VIRTUAL LIBRARIES;

COMBINATORIAL CIRCUITS;

EID: 34748874921     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228857     Document Type: Conference Paper

References (20)

1. K. Keutzer, "Dagon: Technology binding and local optimization by DAG matching", In Proc of the 24th Design Automation Conference, June 1987, pp. 341-347.
2. E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness, "Logic decomposition during technology", IEEE Transactions on Computer-Aided Design, August 1997, 16(8):813-834.
3. Y. Kukimoto, R.K. Brayton, and P. Sawkar, "Delay-optimal technology mapping by DAG covering", In Proc of the DAC'98, 1998. pp. 348-351.
4. L. Stok, M.A. Iyer, and. A.J. Sullivan, "Wavefront Technology Mapping", In Proc. of the DATE'99, Germany, 1999.
5. F. Mailhot, and G. DeMicheli. "Algorithms for technology mapping based on binary decision diagrams and on Boolean operations", IEEE Transactions on CAD for IC and Systems, vol. 12 n° 5, May 1993, pp. 599-620.
6. M. Berkelaar, and J. Jess, "Technology mapping for standard-cell generators", In Proc. Int. Conf. ComputerAided Design, Santa Clara, CA, Nov. 1988, pp. 470-473.
7. K. Keutzer, K. Kolwicz, and M. Lega, "Impact of library size on the quality of automated synthesis", ICCAD 1987, pp. 120-123.
8. K. Scott, and K. Keutzer, "Improving cell libraries for synthesis", In Proc. of CICC, 1994, pp. 128-131.
9. C. Sechen, and B. Guan, "Large standard cell libraries and their impact on layout area and circuit performance", In Proc. of ICCD, 1996, pp. 378-383.
10. S. Gavrilov, A. Glebov, S. Pullela, S. Moore, A. Dharchoudhury, R. Panda, G. Vijayan, and D. Blaauw, "Library-less synthesis for static CMOS combinational logic circuits", in Proc. of ICCAD, 1997, pp:658 - 662.
11. R. Roy, D. Bhattacharya, and V. Boppana, "Transistor-level optimization of digital designs with flex cells", IEEE Computer, Feb. 2005, pp. 53-61.
12. M. Kanecko and J. Tian, "Concurrent cell generation and mapping for CMOS logic circuits", In Proc. of ASPDAC97, 1997, pp. 247-252.
13. R. Poli, F. Schneider, R. Ribas, and A. Reis. "Unified theory to build cell-level transistor networks from BDDs". In Proc. of SBCCI2003, pp.199-204.
14. K. Tanaka, and Y. Kambayashi,. "Transduction method, for design of logic cell structure", In Proc. of ASPDAC2004, pp. 600-603.
15. F. Schneider, R. Ribas, S. Sapatnekar, and A. Reis, "Exact lower bound for the number of switches in series to implement a combinational logic cell", In Proc of ICCD05, 2005, pp. 357-362.
16. I. Sutherland, B. Sproull, and D. Harris "Logical Effort: Designing Fast CMOS Circuits", Morgan Kaufmann, 1999.
17. E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A. Sangiovanni-Vincentelli, "SIS: A system for sequential circuit synthesis", Technical Report No. UCB/ERL M92/4.1, EECS Department, University of California, Berkeley, 1992.
18. S.Chatterjee, A.Mishchenko, R.Brayton, X.Wang, T.Kam, "Reducing Structural Bias in Technology Mapping". IEEE TCAD, accepted for future publication, 2006.
19. P.McGeer, J.Sanghavi, R.Brayton, A.Sangiovanni-Vicentelli. "ESPRESSO-SIGNATURE: a new exact minimizer for logic functions". IEEE Transactions on VLSI, Volume 1, Issue 4, Dec. 1993 Pp:432 - 440.
20. Z.Xiu, D.A.Papa, P.Chong, C.Albrecht, A.Kuehlmann, R.A.Rutenbar, I.L.Markov. "Early research experience with OpenAccess gear: an open source development environment for physical design", In Proc. of ISPD05, pp. 94-100.