Concurrent cell generation and mapping for CMOS logic circuits

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1997, Pages 247-252

  Kaneko, Mineo ^a   Tian, Jialin ^a  

^a JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; CMOS INTEGRATED CIRCUITS; CONFORMAL MAPPING; DATABASE SYSTEMS; DYNAMIC PROGRAMMING; OPTIMIZATION;

CONCURRENT CELL GENERATION;

LOGIC CIRCUITS;

EID: 0030645971     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)