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Volumn , Issue , 2007, Pages 2770-2773

Evaluation of high throughput Turbo-Decoder architectures

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; DECODING; ERROR CORRECTION; THROUGHPUT;

EID: 34548853442     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378627     Document Type: Conference Paper
Times cited : (12)

References (13)
  • 2
    • 14244268187 scopus 로고    scopus 로고
    • Third Generation Partnership Project
    • Third Generation Partnership Project, "3GPP home page," www.3gpp.org.
    • 3GPP home page
  • 5
    • 0034515302 scopus 로고    scopus 로고
    • A High-Speed MAP Architecture with Optimized Memory Size and Power Consumption
    • Lafayette, Louisiana, USA, Oct
    • A. Worm, H. Lamm, and N. Wehn, "A High-Speed MAP Architecture with Optimized Memory Size and Power Consumption," in Proc. 2000 Workshop on Signal Processing Systems (SiPS '00), Lafayette, Louisiana, USA, Oct. 2000, pp. 265-274.
    • (2000) Proc. 2000 Workshop on Signal Processing Systems (SiPS '00) , pp. 265-274
    • Worm, A.1    Lamm, H.2    Wehn, N.3
  • 10
    • 4344646533 scopus 로고    scopus 로고
    • Y. Zhang and K. K. Parhi, Parallel Turbo Decoding, in Proc. 2004 International Symposium on Circuits and Systems (ISCAS '04), Vancouver, Canada, may 2004, pp. II-509-II-512.
    • Y. Zhang and K. K. Parhi, "Parallel Turbo Decoding," in Proc. 2004 International Symposium on Circuits and Systems (ISCAS '04), Vancouver, Canada, may 2004, pp. II-509-II-512.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.