Clock-skew constrained cell placement

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 146-149

  Natesan, V ^a   Bhatia, Dinesh ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MATHEMATICAL PROGRAMMING; SET THEORY; VLSI CIRCUITS;

CLOCK ROUTING TREE; CLOCK SKEW CONSTRAINED CELL PLACEMENT; FIELD PROGRAMMABLE GATE ARRAYS; HIGH LEVEL SYNTHESIS; QUADRATIC PROGRAMMING;

TIMING CIRCUITS;

EID: 0029721378     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)