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Volumn , Issue , 2000, Pages 15-20
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On testing the path delay faults of a microprocessor using its instruction set
a
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
COMBINATORIAL CIRCUITS;
CORRELATION METHODS;
ELECTRIC NETWORK ANALYSIS;
FLIP FLOP CIRCUITS;
INTEGRATED CIRCUIT TESTING;
CONSTRAINT EXTRACTION PROCESS;
DELAY DEFECTS;
FUNCTIONALLY UNTESTABLE PATHS;
INSTRUCTION SET;
K CYCLE TOLERANT PATHS;
PATH CLASSIFICATION;
PATH DELAY FAULTS;
MICROPROCESSOR CHIPS;
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EID: 0033751144
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Article |
Times cited : (44)
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References (9)
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