On testing the path delay faults of a microprocessor using its instruction set

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 15-20

  Lai, Wei Cheng ^a   Krstic, Angela ^a   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; CORRELATION METHODS; ELECTRIC NETWORK ANALYSIS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING;

CONSTRAINT EXTRACTION PROCESS; DELAY DEFECTS; FUNCTIONALLY UNTESTABLE PATHS; INSTRUCTION SET; K CYCLE TOLERANT PATHS; PATH CLASSIFICATION; PATH DELAY FAULTS;

MICROPROCESSOR CHIPS;

EID: 0033751144     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (9)