Instruction-Based delay fault self-testing of pipelined processor cores

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 5686-5689

  Singh, Virendra ^a,c   Inoue, Michiko ^a   Saluja, Kewal K ^b   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

^c CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL CONSTRAINTS; DELAY FAULTS; DELAY-FAULT TESTING; GRAPH MODEL; GRAPH-THEORETIC MODELS; INSTRUCTION SET; MODE OF OPERATIONS; MODERN PROCESSORS; PIPELINED ARCHITECTURE; PIPELINED PROCESSOR; PROCESSOR CORES; SELF-TEST; SELF-TESTING; TEST GENERATIONS; TEST PROGRAM;

COMPUTER ARCHITECTURE; PROGRAM PROCESSORS; TESTING;

PIPELINE PROCESSING SYSTEMS;

EID: 33746865199     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465928     Document Type: Conference Paper

References (9)

1. S.M. Thatte and J. Abraham, "Test generation for Microprocessors", IEEE Trans. on Computers, Vol. C-29, No.6, June 1980, pp. 429-441.
2. L. Chen, S. Ravi, A. Raghunath, and S. Dey, "A Scalable Software-Based Self-Test Methodology for Programmable Processors", Proc. of the Design Automation Conference 2003, pp. 548-553.
3. N .Kranitis, G. Xenoulis, A. Paschalis, D. Gizopolous, Y. Zorian, "Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores", Proc. of International Test Conference, 2003, pp 431-440.
4. W.-C. Lai, A. Krstic, and K.-T. Cheng, "Test Program Synthesis for Path Delay Faults in Microprocessor Cores", Proc. of International Test Conference 2000, pp 1080-1089.
5. V. Singh, M. Inoue, K.K. Saluja, and H. Fujiwara, "Instruction-Based Delay Fault Testing of Processor Cores", Proc. of the International Conference on VLSI Design 2004, pp 933-938.
6. V. Singh, M. Inoue, K.K. Saluja, and H. Fujiwara, "Delay Fault Testing of Processor Cores in Functional Mode", IEICE Trans. on Information & Systems, Vol. E-88D, No. 3, pp 1-9.
7. A. Krstic and K.-T. Cheng, Delay fault testing for VLSI circuits, Kluwer Academic Publishers, 1998.
8. J.L. Hennesy, and D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, 1996.
9. V. Singh, M. Inoue, K.K. Saluja, and H. Fujiwara, "Instruction-Based Delay Fault Self-Testing of Pipelined Processor Cores", NAIST Technical report. http://isw3.aist-nara.ac.jp/IS/TechReport/2004006.