High-level synthesis of HW tasks targeting run-time reconflgurable FPGAs

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM

Volumn , Issue , 2007, Pages

  Boden, Maik ^a   Fiebig, Thomas ^a   Meißner, Torsten ^a   Rülke, Steffen ^a   Becker, Jürgen ^b  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED CIRCUITS   (Germany)

^b UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

GRAPH THEORY; MATHEMATICAL MODELS; OPTIMIZATION;

HIERARCHICAL OPERATIONS; RECONFLGURABLE SYSTEMS; REGISTER-TRANSFER-LEVEL (RTL);

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34548745689     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2007.370390     Document Type: Conference Paper

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