Cross-level hierarchical high-level synthesis

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 451-456

  Bringmann, Oliver ^a,b   Rosenstiel, Wolfgang ^a,b  

^a UNIVERSITY OF KARLSRUHE   (Germany)

^b UNIVERSITY OF TÜBINGEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC SELECTION; COMPLEX COMPONENTS; CROSS LEVELS; EFFICIENT SYNTHESIS; HIERARCHICAL LEVEL; HIERARCHICAL STRUCTURES; HIGH LEVEL SYNTHESIS; NEW APPROACHES;

DESIGN;

HIERARCHICAL SYSTEMS;

EID: 34247161147     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655897     Document Type: Conference Paper

References (18)

1. R. Bergamaschi: Productivity Issues in High-Level Design: Are Tools Solving the Real Problems?. Proceedings of DAC, 1995.
2. M. McFarland, T. Kowalski: Incorporating Bottom-Up Design into Hardware Synthesis. IEEE Transactions on CAD, vol. 9, 1990.
3. D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn: Algorithmic and Register-Transfer Synthesis: The System Architects Workbench. Kluwer, 1990.
4. T. Ly, D. Knapp, R. Miller, D. MacMillen: Scheduling using Behavioral Templates. Proceedings of DAC, 1995.
5. D. Sreenivasa Rao, F. Kurdahi: Hierarchical Design Space Exploration for a Class of Digital Systems. IEEE Transactions on CAD, vol. 1, pp. 282-295, 1993.
6. W. Geurts, F. Catthoor, H. De Man: Quadratic Zero-One Programming-Based Synthesis of Application-Specific Data Paths. IEEE Transactions on CAD, vol. 14, pp. 1-11, 1995.
7. D. C. Ku, G. De Micheli: High-Level Synthesis of ASICs Under Timing and Synchronization Constraints. Kluwer, 1992.
8. P. Kission, H. Ding, A. Jerraya: VHDL Based Design Methodology for Hierarchy and Component Re-Use. Proceedings of EUROVHDL, 1995.
9. B. Landwehr, P. Marwedel, R. Dömer: OSCAR: Optimum Simultaneous Scheduling, Allocation and Resource Binding Based on Integer Programming, Proceedings of EURO-VHDL, 1994.
10. R. Ang: Library Insertion and Reuse of Datapath Components in High-Level Synthesis. PhD Thesis, University of California, Irvine, 1996.
11. B. G. Hald, J. Madsen: A Flexible Representation for High-Level Synthesis. Proceedings of 2nd Asian Pacific Conference on Hardware Description Languages, 1994.
12. P. Jha, N. Dutt: Design Reuse through High-Level Library Mapping. Proceedings of European Design &Test Conference, 1995.
13. O. Bringmann, W. Rosenstiel: Resource Sharing in Hierarchical Synthesis. Proceedings of ICCAD, 1997.
14. W. Rosenstiel, H. Krämer: Scheduling and Assignment in High-Level Synthesis. In R. Camposano, W. Wolf: High-Level VLSI Synthesis, Kluwer, 1991.
15. P. Gutberlet, J. Müller, H. Krämer, W. Rosenstiel: Automatic Module Allocation in High-Level Synthesis. Proc. of EURO-DAC, 1992.
16. P. Gutberlet, H. Krämer, W. Rosenstiel: CASCH-A Scheduling Algorithm for High-Level Synthesis. Proceedings of EDAC, 1991.
17. P. Gutberlet, W. Rosenstiel: Timing Preserving Interface Transformations for the Synthesis of Behavioral VHDL. Proceedings of EURO-VHDL, 1994.
18. B. Eschermann, O. Haberl, O. Bringmann, O. Seitz: COSIMA: A Self-Testable Simulated Annealing Processor for Universal Cost Functions. Proceedings of EuroASIC, 1992.