FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator

Proceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002

Volumn , Issue , 2002, Pages 85-92

  Yi, Ying ^a   Woods, R ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

Architectural DSP Synthesis Tools; FPGA implementation; LMS filfer; System Level Tools

Indexed keywords

ADAPTIVE FILTERS; DESIGN; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE HARDWARE;

ARCHITECTURAL SYNTHESIS; FPGA IMPLEMENTATIONS; INTELLECTUAL PROPERTY CORES; LMS FILFER; SYNTHESIS TOOL; SYSTEM GENERATOR; SYSTEM LEVEL DESIGN; SYSTEM LEVELS;

INTEGRATED CIRCUIT DESIGN;

EID: 1842434133     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2002.1188668     Document Type: Conference Paper

References (9)

1. J. Hwang, B. Milne, N. Shirazi, and J. D. Stroomer, "System Level Tools for DSP in FPGAs", Proc. of 11th Int'l Conf. On Field Programmable Logic (FPL2001), Belfast, UK, August 2001, pp534-543.
2. D. Trainor, R. F. Woods and J. V. McCanny, "Architectural Synthesis of Digital Signal Processing Algorithms using IRIS", Journal of VLSI Signal Processing, Vol. 16, No 1, May 1997, pp41-56.
3. User Guide, Xilinx Blockset Reference Guide, Xilinx System Generator v2.1 for Simulink, 2002.
4. S.Y. Kung, "VLSI Array Processors", Prentice-Hall, Englewood Cliffs, New Jersey, USA, 1988.
5. Appendix B, SIMULINK Dynamic System Simulation for MATLAB (Version 4), Nov. 2000.
6. Y. Yi, R. Woods, L. K. Ting and C. F. N. Cowan, "High Sampling Rate Retimed DLMS Filter Implementations in Virtex-II FPGA", IEEE Workshop on Signal Processing Systems (SIPS'2002), San Diego, California, Oct. 2002, pp139-145.
7. N.Christofides, "Graph Theory - An Algorithmic Approach", Academic Press, London, 1975.
8. C.E.Leiserson, F.M.Rose and J.B.Saxe, "Optimizing Synchronous Circuitry by Retiming", Proc. of the Third Caltech Conference on VLSI, 1983.
9. L.K. Ting, R.F. Woods, C. F. N. Cowan, P. Cork and C, Sprigings, "High-performance fine-grained pipelined LMS algorithm in Virtex FPGA," Proc. of Advanced Signal Processing Algorithms, Architectures, and Implementations X: SPIE, San Diego, USA, Vol. 4116, Aug. 2000, pp. 288-299.