A high-level target-precise model for designing reconfigurable HW tasks

20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Volumn 2006, Issue , 2006, Pages

  Boden, Maik ^a   Rülke, Steffen ^a   Becker, Jürgen ^b  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED CIRCUITS   (Germany)

^b UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; HIGH LEVEL LANGUAGES; LOGIC DESIGN; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SPECIFICATIONS;

DESIGN PATTERNS; EMBEDDED DIGITAL SYSTEMS; HIGH LEVEL MODELING; RUN TIME RECONFIGURABLE;

EMBEDDED SYSTEMS;

EID: 33847118676     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639438     Document Type: Conference Paper

References (11)

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